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Fu-Wei Chen
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2010 – 2019
- 2019
- [c7]Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang:
Crosstalk-aware TSV-buffer Insertion in 3D IC. SoCC 2019: 400-405 - 2014
- [j3]Fu-Wei Chen, TingTing Hwang:
Clock-Tree Synthesis with Methodology of Reuse in 3D-IC. ACM J. Emerg. Technol. Comput. Syst. 10(3): 22:1-22:22 (2014) - [c6]Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang:
Fault-tolerant TSV by using scan-chain test TSV. ASP-DAC 2014: 658-663 - 2012
- [j2]Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang:
A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2255-2264 (2012) - [c5]Fu-Wei Chen, TingTing Hwang:
Clock tree synthesis with methodology of re-use in 3D IC. DAC 2012: 1094-1099 - 2011
- [c4]Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang:
A physical-location-aware fault redistribution for maximum IR-drop reduction. ASP-DAC 2011: 701-706 - 2010
- [j1]Fu-Wei Chen, Yi-Yu Liu:
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 2046-2050 (2010)
2000 – 2009
- 2009
- [c3]Fu-Wei Chen, Yi-Yu Liu:
Performance-driven dual-rail insertion for chip-level pre-fabricated design. DATE 2009: 308-311 - [c2]Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu:
Buffer design and optimization for lut-based structured ASIC design styles. ACM Great Lakes Symposium on VLSI 2009: 377-380 - 2008
- [c1]Fu-Wei Chen, Yi-Yu Liu:
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. DATE 2008: 796-799
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