research-article

Clock tree synthesis with methodology of re-use in 3D IC

Authors:

TingTing HwangAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 1094 - 1099

https://doi.org/10.1145/2228360.2228559

Published: 03 June 2012 Publication History

Abstract

IP reuse methodology has been used extensively in SoC (System on Chip) design. In this reuse methodology, while design and implementation cost is saved, manufacturing cost is not. To further reduce the cost, this reuse concept has been proposed at mask and die level in three-dimension integrated circuit (3D IC). In order to achieve manufacturing reuse, in this paper, we propose a new methodology to design a global clock tree in 3D IC. The objective is to extend an existing clock tree in 2D IC to 3D IC taking into consideration the wirelength, clock skew and the number of TSVs. Compared with NNG-based method, our proposed method reduces the wirelength of the new die and skew of the global 3D clock tree, on an average, 47.16% and 5.85%, respectively.

References

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Cited By

Murali GPark HQin ETorun HDolatsara MSwaminathan MKrishna TLim S(2021)Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.305830029:4(605-616)Online publication date: Apr-2021
https://doi.org/10.1109/TVLSI.2021.3058300
Alure SRamavankateswaran NBuddi RKumar V(2021)Clock Power Reduction Using NDR RoutingProceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems10.1007/978-981-16-0275-7_50(617-625)Online publication date: 10-Sep-2021
https://doi.org/10.1007/978-981-16-0275-7_50
Mondal KChatterjee SSamanta T(2018)An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D ICIET Computers & Digital Techniques10.1049/iet-cdt.2018.510513:2(102-109)Online publication date: 27-Nov-2018
https://doi.org/10.1049/iet-cdt.2018.5105
Show More Cited By

Index Terms

Clock tree synthesis with methodology of re-use in 3D IC
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Information

Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

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National Science Council Taiwan

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DAC '12

Sponsor:

EDAC
SIGDA

DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Citations

Cited By

Murali GPark HQin ETorun HDolatsara MSwaminathan MKrishna TLim S(2021)Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.305830029:4(605-616)Online publication date: Apr-2021
https://doi.org/10.1109/TVLSI.2021.3058300
Alure SRamavankateswaran NBuddi RKumar V(2021)Clock Power Reduction Using NDR RoutingProceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems10.1007/978-981-16-0275-7_50(617-625)Online publication date: 10-Sep-2021
https://doi.org/10.1007/978-981-16-0275-7_50
Mondal KChatterjee SSamanta T(2018)An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D ICIET Computers & Digital Techniques10.1049/iet-cdt.2018.510513:2(102-109)Online publication date: 27-Nov-2018
https://doi.org/10.1049/iet-cdt.2018.5105
Tsai C(2016)2.5D X-Clock Tree Construction Based on Stacked-Layer Combination of Multivoltage Islands2016 International Symposium on Computer, Consumer and Control (IS3C)10.1109/IS3C.2016.118(443-446)Online publication date: Jul-2016
https://doi.org/10.1109/IS3C.2016.118
Liu WWang YChen GMa YXie YYang H(2015)Whitespace-Aware TSV Arrangement in 3-D Clock Tree SynthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.235434723:9(1842-1853)Online publication date: Sep-2015
https://doi.org/10.1109/TVLSI.2014.2354347
Park SHeo JKim T(2014)Allocation and optimization of Post-silicon tunable buffers in TSV based heterogeneous 3D ICs2014 International SoC Design Conference (ISOCC)10.1109/ISOCC.2014.7087605(126-127)Online publication date: Nov-2014
https://doi.org/10.1109/ISOCC.2014.7087605
Li XLiu WDu HWang YMa YYang H(2013)Whitespace-aware TSV arrangement in 3D clock tree synthesis2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2013.6654632(115-120)Online publication date: Aug-2013
https://doi.org/10.1109/ISVLSI.2013.6654632

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