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Decomposition of instruction decoders for low-power designs

Authors:

Wu-An Kuo,

Tingting Hwang,

Allen C.-H. WuAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 4

Pages 880 - 889

https://doi.org/10.1145/1179461.1179465

Published: 01 October 2006 Publication History

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Abstract

During the execution of processor instruction, decoding the instructions is a major task in identifying instructions and generating control signals for data paths. In this article, we propose two instruction decoder decomposition techniques for low-power designs. First, by tracing program execution sequences, we propose an algorithm that explores the relations between frequently executed instructions. Second, we propose a two-stage low-power decomposition structure for decoding instructions. Experimental results demonstrate that our proposed techniques achieve an average of 34.18% in power reduction and 12.93% in critical-path delay reduction for the instruction decoder.

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Cited By

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Jain ASingh ASinghal SMudgal AMehra A(2021)A Novel Power Efficient 2:4 Decoder at 16nm2021 International Conference on Computer Communication and Informatics (ICCCI)10.1109/ICCCI50826.2021.9402503(1-4)Online publication date: 27-Jan-2021
https://doi.org/10.1109/ICCCI50826.2021.9402503
Nagpal RSrikant Y(2007)Compiler-assisted instruction decoder energy optimization for clustered VLIW architecturesProceedings of the 14th international conference on High performance computing10.5555/1782174.1782220(405-417)Online publication date: 18-Dec-2007
https://dl.acm.org/doi/10.5555/1782174.1782220
Nagpal RSrikant Y(2007)Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW ArchitecturesHigh Performance Computing – HiPC 200710.1007/978-3-540-77220-0_38(405-417)Online publication date: 2007
https://doi.org/10.1007/978-3-540-77220-0_38
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Index Terms

Decomposition of instruction decoders for low-power designs
1. Computer systems organization
  1. Architectures
    1. Serial architectures
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Hardware-software codesign

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Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 11, Issue 4

October 2006

177 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1179461

Issue’s Table of Contents

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 October 2006

Published in TODAES Volume 11, Issue 4

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Cited By

View all

Jain ASingh ASinghal SMudgal AMehra A(2021)A Novel Power Efficient 2:4 Decoder at 16nm2021 International Conference on Computer Communication and Informatics (ICCCI)10.1109/ICCCI50826.2021.9402503(1-4)Online publication date: 27-Jan-2021
https://doi.org/10.1109/ICCCI50826.2021.9402503
Nagpal RSrikant Y(2007)Compiler-assisted instruction decoder energy optimization for clustered VLIW architecturesProceedings of the 14th international conference on High performance computing10.5555/1782174.1782220(405-417)Online publication date: 18-Dec-2007
https://dl.acm.org/doi/10.5555/1782174.1782220
Nagpal RSrikant Y(2007)Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW ArchitecturesHigh Performance Computing – HiPC 200710.1007/978-3-540-77220-0_38(405-417)Online publication date: 2007
https://doi.org/10.1007/978-3-540-77220-0_38
Wu-An Kuo TingTing Hwang Wu A(2005)Decomposition of instruction decoder for low power designs2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).10.1109/VDAT.2005.1500066(245-248)Online publication date: 2005
https://doi.org/10.1109/VDAT.2005.1500066

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A power-driven multiplication instruction-set design method for ASIPs

[2009] An Instruction Decomposition Method for Reconfigurable Decoders

Reducing instruction bit-width for low-power VLIW architectures