Article

Free access

Combining technology mapping and placement for delay-optimization in FPGA designs

Authors:

Youn-Long LinAuthors Info & Claims

ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Pages 123 - 127

Published: 07 November 1993 Publication History

PDF eReader

References

[1]

R. Murgal, Y. Nishizaki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Logic Synthesis for Programmable Gate Arrays," Proc. 27th DA C, June 1990, pp. 620-625

Digital Library

Google Scholar

[2]

R. J. Francis, J. Rose, and Z. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FP- GAs," Proc. 28th DAC, pp. 227-233, June, 1991.

Digital Library

Google Scholar

[3]

K. Karplus, "Xmap: a Technology Mapper for Table- Lookup Field-Programmable Gate Arrays," Proc, 28th DAC, June 1991, pp.2~0-2~3

Digital Library

Google Scholar

[4]

R. 3. Francis, J. Rose, and Z. Vranesic, "Technology Mapping of Lookup Table-Based FPGA.,~ for Performance," Proc. int'l Conf. Computer-Aided Design, pp. 568-571, Nov., i991.

Google Scholar

[5]

R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Improved Logic Synthesis Algorithms for Table Look Up Architectures," Proc. Int'l Conf. Computer-aided Design, Nov., 1991

Google Scholar

[6]

R. Murgai, N. Shenoy, R. K. Biayton, and A. Sangiovanni-Vincentelli, "Performance Directed Synthesis for Table Look Up Programmable Gate Arrays," Proc. Int'l Conf. Computer-aided Design, Nov., 1991

Google Scholar

[7]

Christos H. Papadimitriou and Kenneth St eiglitz "Combinatorial Optimization: Algorithms and Complexity," Prentice.Hall, Inc., Englewood Cliffs, New Jersey, 1982

Digital Library

Google Scholar

[8]

Kuang-Chien Chen, "DAG-Map : Graph Based FPGA Technology Mapping For Delay Optimization," IEEE Design and Test of Computer, Sep., 1992.

Digital Library

Google Scholar

[9]

Jason Cong, and Yuzheng Ding "An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs," Proc. lnt'l Conf. Computer-azded Design, pp. 48-53, 1992

Digital Library

Google Scholar

Cited By

View all

Taghavi TGhiasi SRanjan ARaje SSarrafzadeh MAlpert, CGroeneveld P(2004)Innovate or perishProceedings of the 2004 international symposium on Physical design10.1145/981066.981099(148-155)Online publication date: 18-Apr-2004
https://dl.acm.org/doi/10.1145/981066.981099
Wang MRanjan ARaje S(2003)Multi-Million Gate FPGA Physical Design ChallengesProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009992Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009992
Cong JXu SYoshida K(2000)Invited talkProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368596(157-162)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368596
Show More Cited By

Recommendations

Combining technology mapping and placement for delay-minimization in FPGA designs

We combine technology mapping and placement into a single procedure, M.Map, for the design of RAM-based FPGAs. Iteratively, M.Map maps several subnetworks of a Boolean network into a number of CLBs on the layout plane simultaneously. For every output ...
Placement-driven technology mapping for LUT-based FPGAs
FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

In this paper, we study the problem of placement-driven technology mapping for table-lookup based FPGA architectures to optimize circuit performance. Early work on technology mapping for FPGAs such as Chortle-d[14] and Flowmap[3] aim to optimize the ...
Routability-driven technology mapping for lookup table-based FPGA's

A new algorithm for technology mapping of lookup table-based Field-Programmable Gate Arrays (FPGA's) is presented. It has the capability of producing compact designs (minimizing the number of cells (CLB's)), as well as the flexibility of trading ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

November 1993

781 pages

ISBN:0818644907

Chairmen:
Michael Lightner
Univ. of Colorado, Boulder
,
Jochen A. G. Jess
Eindhoven Univ. of Tech., Eindhoven, The Netherlands

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 07 November 1993

Check for updates

Qualifiers

Article

Conference

ICCAD '93

Sponsor:

SIGDA
IEEE-CS

ICCAD '93: International Conference on Computer Aided Design

November 7 - 11, 1993

California, Santa Clara, USA

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
156
Total Downloads

Downloads (Last 12 months)24
Downloads (Last 6 weeks)4

Reflects downloads up to 16 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Taghavi TGhiasi SRanjan ARaje SSarrafzadeh MAlpert, CGroeneveld P(2004)Innovate or perishProceedings of the 2004 international symposium on Physical design10.1145/981066.981099(148-155)Online publication date: 18-Apr-2004
https://dl.acm.org/doi/10.1145/981066.981099
Wang MRanjan ARaje S(2003)Multi-Million Gate FPGA Physical Design ChallengesProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009992Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009992
Cong JXu SYoshida K(2000)Invited talkProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368596(157-162)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368596
Koch APennino TYoffa E(1996)Module compaction in FPGA-based regular datapathsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240608(471-476)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240608
Koch ARose JEbeling C(1996)Structured design implementationProceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays10.1145/228370.228392(151-157)Online publication date: 15-Feb-1996
https://dl.acm.org/doi/10.1145/228370.228392
Karnik TKang SRudell R(1995)An empirical model for accurate estimation of routing delay in FPGAsProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225059(328-331)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225059
Togawa NSato MOhtsuki TJess JRudell R(1994)A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arraysProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191390(156-163)Online publication date: 6-Nov-1994
https://dl.acm.org/doi/10.5555/191326.191390
Yang HWong DJess JRudell R(1994)Edge-mapProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191387(150-155)Online publication date: 6-Nov-1994
https://dl.acm.org/doi/10.5555/191326.191387

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

Combining technology mapping and placement for delay-minimization in FPGA designs

Placement-driven technology mapping for LUT-based FPGAs

Routability-driven technology mapping for lookup table-based FPGA's