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ISVLSI 2017: Bochum, Germany
- 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017. IEEE Computer Society 2017, ISBN 978-1-5090-6762-6
Session 01 - Digital Circuits and FPGA Based Designs I
- Lucas Machado, Antoni Roca Perez, Jordi Cortadella:
Voltage Noise Analysis with Ring Oscillator Clocks. 1-6 - Chia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, Ding-Ming Kwai:
Resilient Cell-Based Architecture for Time-to-Digital Converter. 7-12 - Martin Van Leussen, Jos Huisken
, Lei Wang, Hailong Jiao, José Pineda de Gyvez:
Reconfigurable Support Vector Machine Classifier with Approximate Computing. 13-18 - Jordan Morris, Pranay Prabhat
Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library. 19-24 - Syed Mohammad Asad Hassan Jafri, Nasim Farahini, Ahmed Hemani:
SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level. 25-31 - Raghava Katreepalli
High Speed Power Efficient Carry Select Adder Design. 32-37
Session 02 - Emerging and Post-CMOS Technologies I
- Sparsh Mittal
Architecting SOT-RAM Based GPU Register File. 38-44 - Shaahin Angizi
RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device. 45-50 - Hafiz Md. Hasan Babu, Lafifa Jamal
Area and Delay Efficient Design of a Quantum Bit String Comparator. 51-56 - Hao Cai, You Wang, Lirida A. B. Naviner
Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. 57-61 - Amr M. S. Tosson, Shimeng Yu
Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems. 62-67 - Edgard Muñoz-Coreas, Himanshu Thapliyal
Design of Quantum Circuits for Galois Field Squaring and Exponentiation. 68-73
Session 03 - System Design and Security I
- Hyunmin Kim, Seokhie Hong, Bart Preneel
STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay. 74-79 - Kaige Jia, Zheyu Liu, Fei Qiao, Xinjun Liu, Qi Wei, Huazhong Yang:
AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion Architecture. 80-85 - Magnus Sundal, Ricardo Chaves
Efficient FPGA Implementation of the SHA-3 Hash Function. 86-91 - Hao Liu, Quentin L. Meunier, Alain Greiner:
Decoupling Translation Lookaside Buffer Coherence from Cache Coherence. 92-97 - Brice Colombier, Lilian Bossuet, David Hély
Centrality Indicators for Efficient and Scalable Logic Masking. 98-103 - Yong Chen, Emil Matús, Gerhard P. Fettweis:
Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection Allocator. 104-109
Session 04 - Digital Circuits and FPGA Based Designs II
- Süleyman Savas, Erik Hertz, Tomas Nordström
Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis. 110-115 - Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal
An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. 116-121 - Dimitrios Balobas, Nikos Konofaos
High-Performance and Energy-Efficient 256-Bit CMOS Priority Encoder. 122-127 - Srivatsa Rangachar Srinivasa, Karthik Mohan, Wei-Hao Chen, Kuo-Hsinag Hsu, Xueqing Li, Meng-Fan Chang, Sumeet Kumar Gupta, John Sampson, Vijaykrishnan Narayanan:
Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via. 128-133 - Muhammed Al Kadi, Benedikt Janßen, Michael Hübner:
Floating-Point Arithmetic Using GPGPU on FPGAs. 134-139 - Chia-Chun Tsai:
Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters. 140-145
Session 05 - Emerging and Post-CMOS Technologies II
- Zipeng Li, Kelvin Yi-Tse Lai, Krishnendu Chakrabarty
Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips. 146-151 - Farhana Parveen
Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device. 152-157 - Haider Alrudainy
Ultra-Low Energy Data Driven Computing Using Asynchronous Micropipelines and Nano-Electro-Mechanical Relays. 158-163 - Eleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini
Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies. 164-169 - Jannis Stoppe
BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips. 170-175 - Lei Xie, Hoang Anh Du Nguyen, Jintao Yu
Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing. 176-181
Session 06 - System Design and Security II
- Shirshendu Das, Hemangee K. Kapoor:
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. 182-187 - Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin, Kapil R. Dandekar
Wireless NoCs Using Directional and Substrate Propagation Antennas. 188-193 - Saleh Usman
A Multi-Gbps Fully Pipelined Layered Decoder for IEEE 802.11n/ac/ax LDPC Codes. 194-199 - Hela Belhadj Amor, Hamed Sheibanyrad, Frédéric Pétrot:
A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoC. 200-205 - Ziyad Almohaimeed
Secured-by-Design FPGA against Early Evaluation. 206-212 - Saru Vig, Tan Yng Tzer, Guiyuan Jiang, Siew-Kei Lam:
Customizing Skewed Trees for Fast Memory Integrity Verification in Embedded Systems. 213-218
Session 07 - Digital Circuits and FPGA Based Designs III
- Mohd. Tasleem Khan, Shaik Rafi Ahamed:
A New High Performance VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic. 219-224 - Oana Boncalo, Alexandru Amaricai:
Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders. 225-230 - Soumya Banerjee, Wenjing Rao
A General Design Framework for Sparse Parallel Prefix Adders. 231-236 - Shang-Rong Fang, Cheng-Wei Tai, Rung-Bin Lin:
On Benchmarking Pin Access for Nanotechnology Standard Cells. 237-242 - Tuba Ayhan, Firat Kula
A Power Efficient System Design Methodology Employing Approximate Arithmetic Units. 243-248
Session 08 - Student Research Forum
- Yimai Peng
A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number Generator. 249-254 - Ali A. Aboughaly, Mohamed A. Abd El Ghany:
Unobtrusive Wearable Health Monitoring System. 255-259 - Sangamesh Kodge, Himanshu Chaudhary, Mrigank Sharad:
Low Power Image Acquisition Scheme Using On-Pixel Event Driven Halftoning. 260-265 - Rakshit Pathak, Saurav Dash, Anand Kumar Mukhopadhyay, Arindam Basu
Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training Engine. 266-271
Session 09 - System Design and Security III
- Lakshmi Bhamidipati, Bhoopal Gunna, Houman Homayoun, Avesta Sasan:
A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews. 272-277 - Tannu Sharma, Kenneth S. Stevens:
Physical Design Variation in Relative Timed Asynchronous Circuits. 278-283 - Johanna Sepúlveda, Mathieu Gross, Andreas Zankl
Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips. 284-289 - Leonel Acunha Guimaraes, Rodrigo Possamai Bastos, Laurent Fesquet:
Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors. 290-295 - Tosiron Adegbija, Ravi Tandon:
Coding for Efficient Caching in Multicore Embedded Systems. 296-301 - Ankur Limaye
A Workload Characterization for the Internet of Medical Things (IoMT). 302-307
Session 10 - Testing, Reliability, and Fault-Tolerance I
- Naixing Wang, Bo Yao, Xijiang Lin, Irith Pomeranz:
Functional Broadside Test Generation Using a Commercial ATPG Tool. 308-313 - Irith Pomeranz:
Static Compaction by Merging of Seeds for LFSR-Based Test Generation. 314-319 - Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh:
Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. 320-325 - Salmen Mraihi, El Mehdi Boujamaa, Cyrille Dray, Jacques-Olivier Klein
Offset Analysis and Design Optimization of a Dynamic Sense Amplifier for Resistive Memories. 326-331 - Stephan Friedrichs, Attila Kinali
Efficient Metastability-Containing Multiplexers. 332-337 - Sarah Azimi
Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach. 338-343
Session 11 - Research Projects
- Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat:
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. 344-349 - George Lentaris, Ioannis Stratakos, Ioannis Stamoulias, Konstantinos Maragos, Dimitrios Soudris, Manolis I. A. Lourakis
Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space. 350-355 - Apostolos P. Fournaris, Konstantinos Lampropoulos
Hardware Security for Critical Infrastructures - The CIPSEC Project Approach. 356-361 - Konstantina Koliogeorgi, Dimosthenis Masouros, Georgios Zervakis, Sotirios Xydis, Tobias Becker
AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics. 362-367 - Marco Rabozzi, Rolando Brondolin, Giuseppe Natale, Emanuele Del Sozzo
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project. 368-373 - Georgios Keramidas, Nikolaos S. Voros
Profile-Driven Power Optimizations for AAL Robots: Maximizing Robots Idle Time by Offloading Monitoring Workload to Dedicated Hardware Components. 374-378
Session 12 - System Design and Security IV
- Alex Pappachen James
Unified Model for Contrast Enhancement and Denoising. 379-384 - Marcelo Ruaro
SDN-Based Circuit-Switching for Many-Cores. 385-390 - Rafail Psiakis, Angeliki Kritikakou
NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors. 391-396 - Dan Cristian Turicu, Octavian Cret, Lucia Vacariu:
Serial ATA Commands Logger for Security Monitoring on FPGA Devices. 397-402 - Sam Gianelli, Tosiron Adegbija:
PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems. 403-408 - Taylor J. L. Whitaker, Christophe Bobda:
CAPSL: The Component Authentication Process for Sandboxed Layouts. 409-414
Session 13 - Testing, Reliability, and Fault-Tolerance II
- Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski:
Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis. 415-420 - Shvan Karim, Jim Harkin
Assessing Self-Repair on FPGAs with Biologically Realistic Astrocyte-Neuron Networks. 421-426 - Shuyu Kong, Jie Gu, Hai Zhou:
Memristor-Based Clock Design and Optimization with In-Situ Tunability. 427-432 - Hamzeh Ahangari, Ihsen Alouani
Reconfigurable Hardened Latch and Flip-Flop for FPGAs. 433-438
Session 14 - Computer-Aided Design and Verification I
- Tung Thanh Le, Dan Zhao, Magdy A. Bayoumi:
Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware Approach. 439-444 - Mohammad Fawaz, Farid N. Najm:
Parallel Simulation-Based Verification of RC Power Grids. 445-452 - Ming Yan, Yici Cai, Chenguang Wang, Qiang Zhou:
An Effective Power Grid Optimization Approach for the Electromigration Reliability. 453-458 - Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, Ding-Ming Kwai, Yung-Fa Chou:
On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC. 459-464 - Scott Lerner, Baris Taskin:
WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS. 465-470 - Tong Zhang, Daniel G. Saab, Jacob A. Abraham:
Automatic Assertion Generation for Simulation, Formal Verification and Emulation. 471-476
Session 15 - System Design and Security V
- Vasilios I. Kelefouras, Georgios Keramidas, Nikolaos S. Voros
Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management. 477-482 - Sri Harsha Gade, Sakshi Garg, Sujay Deb
OFDM Based High Data Rate, Fading Resilient Transceiver for Wireless Networks-on-Chip. 483-488 - Luca Cremona, William Fornaciari
DENA: A DVFS-Capable Heterogeneous NoC Architecture. 489-494 - Chenxi Dai, Tosiron Adegbija:
Exploiting Configurability as a Defense against Cache Side Channel Attacks. 495-500
Session 16 - Analog and Mixed-Signal Circuits I
- Shuo Li, Xiaolin Xu, Wayne P. Burleson:
CCATDC: A Configurable Compact Algorithmic Time-to-Digital Converter. 501-506 - Hong Liu, Zheyu Liu, Fei Qiao, Mark Po-Hung Lin
AIsim: Functional Simulator for Analog-to-Information Perceptual Systems. 507-512 - Mousumi Bhanja
A Hierarchical and Programmable OTA-C Filter. 513-518 - Ming-Yu Huang, Ren-Yuan Huang, Ro-Min Weng:
A 0.3V Low Cost Low Power 24 GHz Low Noise Amplifier with Body Bias Technology. 519-522 - Hua Fan, Franco Maloberti, Dagang Li, Daqian Hu, Yuanjun Cen, Hadi Heidari
Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC. 523-528 - Keunyeol Park, Ohoon Kwon, Hyunseob Noh, Minhyun Jin, Minkyu Song:
Design of an Asynchronous Detector with Priority Encoding Technique. 529-532
Session 17 - Computer-Aided Design and Verification II
- Tino Flenker, Jan Malburg, Görschwin Fey
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. 533-538 - Melanie Brocard, Benoît Mathieu, Jean-Philippe Colonna, Cristiano Santos, Claire Fenouillet-Béranger, Cao-Minh Vincent Lu, Gerald Cibrario, Laurent Brunet, Perrine Batude, François Andrieu, Sébastien Thuries, Olivier Billoint:
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells. 539-544 - Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi:
Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. 545-550 - Hamed Hossein-Talaee, Ali Jahanian:
Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space Distribution. 551-555 - Tomás Grimm, Djones Lettnin, Michael Hübner:
Semiformal Verification of Software-Controlled Connections. 556-561
Special Session 01 - Post CMOS Computing: Emerging Technologies and Design Issues
- Zhou Zhao, Xinlu Chen, Ashok Srivastava, Lu Peng, Saraju P. Mohanty:
Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design. 562-567 - Mayukh Sarkar
Performing Mathematics Using DNA: Complex Number Arithmetic Using Sticker Model. 568-573 - Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
Analysis of Side-Channel Attack AES Hardware Trojan Benchmarks against Countermeasures. 574-579
Session 18 - Analog and Mixed-Signal Circuits II
- Ali H. Hassan
A VCO-Based MPPT Circuit for Low-Voltage Energy Harvesters. 580-584 - Sumit Khalapure
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. 585-588 - Rakhi R., Abhijeet D. Taralkar, M. H. Vasantha, Kumar Y. B. Nithin
A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection. 589-593 - Greeshma R, Anoop V. K, B. Venkataramani:
A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology. 594-599 - S. M. Mayur, Siddharth R. K.
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. 600-603 - Hossam ElGemmazy, Amr Helmy, Hassan Mostafa
A Novel CMOS-Based Fully Differential Operational Floating Conveyor. 604-608
Special Session 02 - Emerging Computing Paradigms for Energy-Efficient and Secure IoT Devices
- Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh
Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function. 609-614 - Garrett S. Rose
Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices. 615-620 - Himanshu Thapliyal
Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices. 621-626
Special Session 03 - Adaptive Circuits and Systems for Machine Intelligence: The Role of Adaptive Circuits and Systems in Emerging Intelligent Systems and Networks
- Muhammad Shafique
Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. 627-632 - Jens Rettkowski, Diana Göhringer
Data Stream Processing in Networks-on-Chip. 633-638 - Giuseppe Natale, Marco Bacis, Marco Domenico Santambrogio:
On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks. 639-644 - Ruizhe Zhao, Wayne Luk, Xinyu Niu, Huifeng Shi, Haitao Wang:
Hardware Acceleration for Machine Learning. 645-650
Session 19 - Analog and Mixed-Signal Circuits III
- Xingyuan Tong, Kangkang Wei:
A Fully Integrated Fast-Response LDO Voltage Regulator with Adaptive Transient Current Distribution. 651-654 - Mahesh Kumar Adimulam, Krishna Kumar Movva, K. Kolluru, M. B. Srinivas:
A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications. 655-660 - Andres Amaya, Javier Ardila
A Digital Offset Reduction Method for Dynamic Comparators Based on Phase Measurement. 661-664
Special Session 04 - Emerging and Secured Applications of IoT
- Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh
Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET. 665-670 - Subha Koley, Prasun Ghosal:
An IoT Enabled Real-Time Communication and Location Tracking System for Vehicular Emergency. 671-676 - K. Sudeendra Kumar, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamala Kanta Mahapatra:
A Flexible Pay-per-Device Licensing Scheme for FPGA IP Cores. 677-682
Special Session 05 - Innovation in Memory Technologies and Their Applications
- Deliang Fan, Shaahin Angizi
In-Memory Computing with Spintronic Devices. 683-688 - Lita Yang, Boris Murmann
Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks. 689-694
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