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Rung-Bin Lin
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2020 – today
- 2024
- [c54]Rung-Bin Lin, Pei-Sheng Lu:
Sub-10nm Standard Cell Library Design Methodology for On-Grid Pin Accesses. ISCAS 2024: 1-5 - [c53]Po-Chun Wang, Kai-Jie Ton, Rung-Bin Lin:
Routing Intent Aware Pin Access Point Selection for Standard Cell Designs. ISQED 2024: 1-8 - 2023
- [c52]Pei-Sheng Lu, Rung-Bin Lin:
Improving Pin Accessibility of Standard Cells under Power/Ground Stripes. NEWCAS 2023: 1-5 - 2022
- [c51]Tsao-Hsuan Peng, Chih-Chun Hsu, Po-Chun Wang, Rung-Bin Lin:
Improving Pin Accessibility of Standard Cell Libraries in 7nm Technology. ISQED 2022: 1-6 - 2021
- [c50]Tzu-Hsuan Wang, Chih-Chun Hsu, Li Kao, Bing-Yu Li, Tung-Chun Wu, Tsao-Hsuan Peng, Rung-Bin Lin:
Six-track Standard Cell Libraries with Fin Depopulation, Contact over Active Gate, and Narrower Diffusion Break in 7nm Technology. ISQED 2021: 361-366 - 2020
- [c49]Yuan-Dar Chung, Rung-Bin Lin:
Engineering a Standard Cell Library for an Industrial Router with ASAP7 PDK. ISVLSI 2020: 404-409
2010 – 2019
- 2019
- [c48]Rung-Bin Lin, Yu-Xiang Chiang:
Impact of Double-Row Height Standard Cells on Placement and Routing. ISQED 2019: 317-322 - [c47]Cheng-Wei Tai, Rung-Bin Lin:
Morphed Standard Cell Layouts for Pin Length Reduction. ISVLSI 2019: 94-99 - 2018
- [j15]Kuen-Wey Lin
, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin:
A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction. ACM Trans. Design Autom. Electr. Syst. 23(4): 45:1-45:26 (2018) - [c46]Yu-Cheng Chiang, Shr-Cheng Tsai, Rung-Bin Lin:
Recognition of regular layout structures. ISQED 2018: 75-81 - [c45]Yu-Xiang Chiang, Cheng-Wei Tai, Shang-Rong Fang, Kai-Chun Peng, Yuan-Dar Chung, Jin-Kai Yang, Rung-Bin Lin:
Designing and Benchmarking of Double-Row Height Standard Cells. ISVLSI 2018: 64-69 - 2017
- [c44]Kuen-Wey Lin
A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points. ACM Great Lakes Symposium on VLSI 2017: 399-402 - [c43]Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake:
Overview of the 2017 CAD contest at ICCAD: Invited paper. ICCAD 2017: 855-856 - [c42]Shang-Rong Fang, Cheng-Wei Tai, Rung-Bin Lin:
On Benchmarking Pin Access for Nanotechnology Standard Cells. ISVLSI 2017: 237-242 - 2016
- [c41]Kuen-Wey Lin
Multiple-patterning lithography-aware routing for standard cell layout synthesis. APCCAS 2016: 534-537 - [c40]Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin, Rung-Bin Lin:
Practical ILP-based routing of standard cells. DATE 2016: 245-248 - [c39]Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake:
Overview of the 2016 CAD contest at ICCAD. ICCAD 2016: 38 - [c38]Chi-Hung Lin, Chia-Shiang Chen, Yu-He Chang, Yu Ting Zhang, Shang-Rong Fang, Santanu Santra, Rung-Bin Lin:
Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library. ISVLSI 2016: 673-678 - 2015
- [c37]Ang Lu, Hsueh-Ju Lu, En-Jang Jang, Yu-Po Lin, Chun-Hsiang Hung, Chun-Chih Chuang, Rung-Bin Lin:
Simultaneous transistor pairing and placement for CMOS standard cells. DATE 2015: 1647-1652 - [c36]Natarajan Viswanathan, Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim:
Overview of the 2015 CAD Contest at ICCAD. ICCAD 2015: 910-911 - [c35]Chiung-Chih Ho, Hsin-Pei Tsai, Liang-Chi Lai, Rung-Bin Lin:
A router for via configurable structured ASIC with standard cells and relocatable IPs. ISQED 2015: 51-56 - 2014
- [c34]Ta-Kai Lin, Kuen-Wey Lin
Logic block and design methodology for via-configurable structured ASIC using dual supply voltages. ACM Great Lakes Symposium on VLSI 2014: 111-116 - [c33]Jian Zeng, Jian-Yang Zhou, Rung-Bin Lin:
Transition inversion coding with parity check for off-chip serial transmission. ICECS 2014: 634-637 - 2013
- [c32]Chia-Chieh Lu, Rung-Bin Lin:
Slack budgeting and slack to length converting for multi-bit flip-flop merging. DATE 2013: 1837-1842 - [c31]Hsin-Hung Liu, Rung-Bin Lin, I-Lun Tseng:
Relocatable and resizable SRAM synthesis for via configurable structured ASIC. ISQED 2013: 494-501 - 2012
- [j14]Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang:
$2^{n}$ Pattern Run-Length for Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 644-648 (2012) - [j13]Hui-Hsiang Tung, Rung-Bin Lin, Mei-Chen Li, Tsung-Han Heish:
Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2184-2197 (2012) - [c30]Hsin-Pei Tsai, Rung-Bin Lin, Liang-Chi Lai:
Design and analysis of via-configurable routing fabrics for structured ASICs. DATE 2012: 1479-1482 - 2011
- [c29]Shih-Jung Hsu, Rung-Bin Lin:
Clock gating optimization with delay-matching. DATE 2011: 643-648 - [c28]Liang-Chi Lai, Hsih-Hang Chang, Rung-Bin Lin:
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs. ACM Great Lakes Symposium on VLSI 2011: 37-42 - 2010
- [j12]Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin:
Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction. IET Comput. Digit. Tech. 4(4): 317-324 (2010) - [c27]Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin
Power gating design for standard-cell-like structured ASICs. DATE 2010: 514-519 - [c26]Yu-Chen Chen, Hou-Yu Pang, Kuen-Wey Lin
Via configurable three-input lookup-tables for structured ASICs. ACM Great Lakes Symposium on VLSI 2010: 49-54 - [c25]Rung-Bin Lin, I-Wei Lee, Wen-Hao Chen:
Clock routing for structured ASICs with via-configurable fabrics. ISQED 2010: 777-784
2000 – 2009
- 2009
- [c24]Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu:
Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing. Asian Test Symposium 2009: 111-116 - [c23]Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee:
A Multi-dimensional Pattern Run-Length Method for Test Data Compression. Asian Test Symposium 2009: 325-330 - [c22]Po-Heng Chu, Rung-Bin Lin, Da-Wei Hsu, Yu-Hsing Chen, Wei-Chiu Tseng:
Context-aware Post Routing Redundant Via Insertion. ISVLSI 2009: 37-42 - 2008
- [j11]Rung-Bin Lin:
Variable-sized object packing and its applications to instruction cache design. Comput. Electr. Eng. 34(5): 438-444 (2008) - [j10]Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin:
Power Reduction during Scan Testing Based on Multiple Capture Technique. IEICE Trans. Electron. 91-C(5): 798-805 (2008) - [j9]Meng-Chiou Wu, Rung-Bin Lin:
Finding Dicing Plans for Multiple Project wafers fabricated with Shuttle Mask. J. Circuits Syst. Comput. 17(1): 15-31 (2008) - [j8]Rung-Bin Lin:
Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1911-1920 (2008) - [j7]Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai:
Chip placement in a reticle for multiple-project wafer fabrication. ACM Trans. Design Autom. Electr. Syst. 13(1): 22:1-22:21 (2008) - [c21]Wei-Chiu Tseng, Yu-Hsing Chen, Rung-Bin Lin:
Router and cell library co-development for improving redundant via insertion at pins. ICCD 2008: 646-651 - [c20]Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin:
Standard Cell Like Via-Configurable Logic Block for Structured ASICs. ISVLSI 2008: 381-386 - 2007
- [j6]Rung-Bin Lin, Shuyu Chen:
Conjugate conflict continuation graphs for multi-layer constrained via minimization. Inf. Sci. 177(12): 2436-2447 (2007) - [j5]Rung-Bin Lin, Meng-Chiou Wu, Shih-Cheng Tsai:
Reticle Design for Minimizing Multiproject Wafer Production Cost. IEEE Trans Autom. Sci. Eng. 4(4): 589-595 (2007) - [c19]Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin:
Double-via-driven standard cell library design. DATE 2007: 1212-1217 - [c18]Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu:
Reticle Exposure Plans for Multi-Project Wafers. DDECS 2007: 341-344 - 2006
- [c17]Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai:
Design space exploration for minimizing multi-project wafer production cost. ASP-DAC 2006: 783-788 - [c16]Hsun-Chieh Yu, Rung-Bin Lin:
Is more redundancy better for on-chip bus encoding. ISCAS 2006 - 2005
- [c15]Meng-Chiou Wu, Rung-Bin Lin:
Reticle floorplanning of flexible chips for multi-project wafers. ACM Great Lakes Symposium on VLSI 2005: 494-497 - [c14]Guang-Wan Liao, Ja-Shong Feng, Rung-Bin Lin:
A divide-and-conquer approach to estimating minimum/maximum leakage current. ISCAS (5) 2005: 4717-4720 - [c13]Meng-Chiou Wu, Rung-Bin Lin:
Multiple project wafers for medium-volume IC production. ISCAS (5) 2005: 4725-4728 - [c12]Rung-Bin Lin:
Coupling reduction analysis of bus-invert coding. ISCAS (6) 2005: 5862-5865 - [c11]Meng-Chiou Wu, Rung-Bin Lin:
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. ISQED 2005: 610-615 - [c10]Meng-Chiou Wu, Rung-Bin Lin:
A Comparative Study on Dicing of Multiple Project Wafers. ISVLSI 2005: 314-315 - 2004
- [c9]Rung-Bin Lin, Shuyu Chen:
Multi-layer constrained via minimization with conjugate conflict continuation graphs. ISCAS (4) 2004: 525-528 - 2003
- [c8]Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin:
A Low Power-Delay Product Page-Based Address Bus Coding Method. VLSI Design 2003: 521-526 - 2002
- [j4]Rung-Bin Lin:
Comments on "Filling algorithms and analyses for layout density control". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1209-1211 (2002) - [j3]Rung-Bin Lin, Chi-Ming Tsai:
Theoretical analysis of bus-invert coding. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 929-934 (2002) - [c7]Rung-Bin Lin, Chi-Ming Tsai:
Weight-Based Bus-Invert Coding for Low-Power Applications. ASP-DAC/VLSI Design 2002: 121-125 - [c6]Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin:
An Adaptive Interconnect-Length Driven Placer. ASP-DAC/VLSI Design 2002: 393-398
1990 – 1999
- 1999
- [c5]Rung-Bin Lin, Jinq-Chang Chen:
Low Power CMOS Off-Chip Drivers with Slew-rate Difference. ASP-DAC 1999: 169-172 - [c4]Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai:
Benchmark Circuits Improve the Quality of a Standard Cell Library. ASP-DAC 1999: 173-176 - 1998
- [c3]Rung-Bin Lin, Meng-Chiou Wu:
A New Statistical Approach to Timing Analysis of VLSI Circuits. VLSI Design 1998: 507- - 1994
- [j2]Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz:
Fuzzy logic approach to VLSI placement. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 489-501 (1994) - 1993
- [j1]Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin:
An adaptive timing-driven placement for high performance VLSIs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10): 1488-1498 (1993) - 1992
- [c2]Rung-Bin Lin, Eugene Shragowitz:
Fuzzy Logic Approach to Placement Problem. DAC 1992: 153-158 - 1991
- [c1]Habib Youssef, Rung-Bin Lin, Eugene Shragowitz:
Bounds on Net Delays for Physical Design of Fast Circuits. VLSI 1991: 111-118
Coauthor Index
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