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Siddharth R. K.
Person information
- affiliation: National Institute of Technology Goa, Department of Electronics and Communication Engineering, India
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2020 – today
- 2024
- [j6]K. G. Shreeharsha
, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin
An Error Bound Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 12: 50126-50136 (2024) - [j5]Rakhi R., Siddharth R. K., K. G. Shreeharsha, M. H. Vasantha, Nithin Kumar Yernad Balachandra:
N-Parallel Paths-Based D-Latch for High-Speed Applications. IEEE Access 12: 162930-162938 (2024) - 2023
- [j4]K. G. Shreeharsha
Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 11: 123577-123588 (2023) - [c20]R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni:
A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS. ISCAS 2023: 1-5 - [c19]Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran:
Approximate Three-Operand Binary Adder for Error-Resilient Applications. iSES 2023: 287-291 - [c18]Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi:
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. VLSID 2023: 1-6 - 2021
- [c17]Peta Guruprakashkumar, Siddharth R. K.
A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. ISCAS 2021: 1-5 - [c16]Shiv Chandra Kumar, Siddharth R. K.
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications. ISVLSI 2021: 19-24 - [c15]Sanmitra Bharat Naik, Siddharth R. K.
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. VLSID 2021: 252-257 - 2020
- [j3]Siddharth Rajkumar Kala
6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process. IET Circuits Devices Syst. 14(3): 340-346 (2020) - [j2]Siddharth R. K.
Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications. SN Comput. Sci. 1(6): 310 (2020) - [j1]Siddharth R. K.
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications. IEEE Trans. Circuits Syst. 67-II(12): 2918-2922 (2020) - [c14]Nitish Kumar, Siddharth R. K.
A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC. iSES 2020: 167-170 - [c13]Tejas J. Shahane, Siddharth R. K.
A 1.8 V, Mode-Configurable Hybrid Smart ADC. iSES 2020: 216-220 - [c12]Sanmitra Bharat Naik, Siddharth R. K.
A 1.8 V Quadrature Phase LC Oscillator for 5G Applications. iSES 2020: 277-280 - [c11]Suraj Dohar, Siddharth R. K.
A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications. ISVLSI 2020: 48-53 - [c10]Sanmitra Bharat Naik, Siddharth R. K.
A Wideband 12 Phase Ring Oscillator for 5G Applications. MWSCAS 2020: 885-888
2010 – 2019
- 2019
- [c9]Pradeep R., Siddharth R. K.
Process Corner Calibration for Standard Cell Based Flash ADC. iSES 2019: 195-200 - [c8]Rahul E., Siddharth R. K.
Two-Step Flash ADC Using Standard Cell Based Flash ADCs. iSES 2019: 292-295 - [c7]Sunil R., Siddharth R. K.
An Asynchronous Analog to Digital Converter for Video Camera Applications. ISVLSI 2019: 175-180 - 2018
- [c6]Siddharth R. K.
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. ISCAS 2018: 1-5 - [c5]Chetan Kamble, Siddharth R. K.
Design of Area-Power-Delay Efficient Square Root Carry Select Adder. iSES 2018: 80-85 - [c4]Siddharth R. K.
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications. ISVLSI 2018: 164-169 - 2017
- [c3]Sumit Khalapure
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. ISVLSI 2017: 585-588 - [c2]S. M. Mayur, Siddharth R. K.
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. ISVLSI 2017: 600-603 - 2016
- [c1]S. M. Mayur, Siddharth R. K.
Design of Low Power 5-Bit Hybrid Flash ADC. ISVLSI 2016: 343-348
Coauthor Index
aka: Nithin Y. B. Kumar
aka: Nithin Kumar Y. B.
aka: Kumar Y. B. Nithin
aka: Y. B. Nithin Kumar
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last updated on 2024-11-19 20:46 CET by the dblp team
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