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Syed M. A. H. Jafri
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2020 – today
- 2023
- [j10]Dimitrios Stathis
, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani:
Clock tree generation by abutment in synchoros VLSI design. Microprocess. Microsystems 102: 104913 (2023) - 2021
- [j9]Syed Mohammad Asad Hassan Jafri, Hasan Hassan, Ahmed Hemani, Onur Mutlu:
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. ACM Trans. Archit. Code Optim. 18(1): 2:1-2:29 (2021) - [c27]Dimitrios Stathis
Clock Tree Generation by Abutment in Synchoros VLSI Design. NorCAS 2021: 1-7
2010 – 2019
- 2019
- [i3]Syed M. A. H. Jafri, Hasan Hassan, Ahmed Hemani, Onur Mutlu:
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. CoRR abs/1910.06672 (2019) - [i2]Dimitrios Stathis
Regional Clock Tree Generation by Abutment in Synchoros VLSI Design. CoRR abs/1910.11253 (2019) - [i1]Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn:
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. CoRR abs/1911.00889 (2019) - 2017
- [c26]Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Leonardo Intesa:
SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUs. DSD 2017: 94-101 - [c25]Yu Yang
MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs. PARMA-DITAM@HiPEAC 2017: 31-36 - [c24]Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Kolin Paul, Naeem Abbas:
MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks. IPDPS 2017: 276-286 - [c23]Syed Mohammad Asad Hassan Jafri, Nasim Farahini, Ahmed Hemani:
SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level. ISVLSI 2017: 25-31 - [c22]Ahmed Hemani, Syed Mohammad Asad Hassan Jafri, Shayesteh Masoumian:
Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable. NOCS 2017: 8:1-8:10 - [c21]Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis
Can a reconfigurable architecture beat ASIC as a CNN accelerator? SAMOS 2017: 97-104 - 2016
- [j8]Syed M. A. H. Jafri, Masoud Daneshtalab
TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs. IEEE Trans. Computers 65(11): 3456-3469 (2016) - [j7]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila
Polymorphic Configuration Architecture for CGRAs. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 403-407 (2016) - [c20]Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peeter Ellervee
TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs. PATMOS 2016: 92-99 - 2015
- [j6]Syed M. A. H. Jafri, Ozan Ozbag, Nasim Farahini, Kolin Paul, Ahmed Hemani, Juha Plosila
Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs. ACM J. Emerg. Technol. Comput. Syst. 11(4): 40:1-40:29 (2015) - [j5]Syed M. A. H. Jafri, Masoud Daneshtalab
TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs. Microprocess. Microsystems 39(8): 973-986 (2015) - [c19]Tuan Ngyen, Syed M. A. H. Jafri, Masoud Daneshtalab, Ahmed Hemani, Sergei Dytckov, Juha Plosila
FIST: A Framework to Interleave Spiking Neural Networks on CGRAs. PDP 2015: 751-758 - [c18]Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Peeter Ellervee
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs. VLSID 2015: 547-552 - 2014
- [j4]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila
Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. 18(3-4): 295-327 (2014) - [j3]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of the coarse-grained reconfigurable architecture DART with on-line error detection. Microprocess. Microsystems 38(2): 124-136 (2014) - [j2]Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Kolin Paul:
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. Microprocess. Microsystems 38(8): 788-802 (2014) - [c17]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee
Morphable Compression Architecture for Efficient Configuration in CGRAs. DSD 2014: 42-49 - [c16]Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee
Customizable Compression Architecture for Efficient Configuration in CGRAs. FCCM 2014: 31 - [c15]Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila
TransPar: Transformation based dynamic Parallelism for low power CGRAs. FPL 2014: 1-8 - [c14]Syed M. A. H. Jafri, Tuan Nguyen Gia
NeuroCGRA: A CGRA with support for neural networks. HPCS 2014: 506-511 - [c13]Hassan Anwar, Syed M. A. H. Jafri, Sergei Dytckov, Masoud Daneshtalab, Masoumeh Ebrahimi, Ahmed Hemani, Juha Plosila, Giovanni Beltrame, Hannu Tenhunen:
Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures. MES 2014: 64-67 - [c12]Syed M. A. H. Jafri, Guilermo Serrano, Junaid Iqbal
RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs. ICSAMOS 2014: 233-241 - 2013
- [j1]Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes. Microprocess. Microsystems 37(8-A): 811-822 (2013) - [c11]Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Juha Plosila
Private configuration environments (PCE) for efficient reconfiguration, in CGRAs. ASAP 2013: 227-236 - [c10]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD 2013: 525-534 - [c9]Syed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells. ISQED 2013: 104-111 - [c8]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC 2013: 1-8 - [c7]Liang Guang, Syed M. A. H. Jafri, Bo Yang, Juha Plosila, Hannu Tenhunen:
Hierarchical Supporting Structure for Dynamic Organization in Many-core Computing Systems. PECCS 2013: 252-261 - [c6]Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila
Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs. ICSAMOS 2013: 104-112 - 2012
- [c5]Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila
Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes. DSD 2012: 242-249 - [c4]Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen:
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. PECCS 2012: 450-458 - 2011
- [c3]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila
Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures. FPT 2011: 1-6 - [c2]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila
Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures. IPDPS Workshops 2011: 290-293 - 2010
- [c1]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys
Design of a fault-tolerant coarse-grained. ISQED 2010: 845-852
Coauthor Index
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