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James Myers
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2020 – today
- 2024
- [j14]Zhenlin Pei
, Hsiao-Hsuan Liu
Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4597-4610 (2024) - [j13]Leandro Mateus Giacomini Rocha, Refik Bilgic, Mohamed Naeim, Sudipta Das, Herman Oprins, Amirreza Yousefzadeh, Mario Konijnenburg, Dragomir Milojevic, James Myers, Julien Ryckaert, Dwaipayan Biswas:
Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2144-2148 (2024) - [c33]Subrat Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, A. Sharma, G. Mirabeli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert:
Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. IRPS 2024: 1-6 - [c32]Nitish Kumar, Sankatali Venkateswarlu, Yukai Chen, Moritz Brunion, Subrat Mishra, Ankur Gupta, Pushpapraj Singh, Francky Catthoor, James Myers, Julien Ryckaert, Dwaipayan Biswas:
Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies. IRPS 2024: 8 - [c31]Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic:
3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. ISCAS 2024: 1-5 - [c30]Dwaipayan Biswas, James Myers, Srikanth B. Samavedam, Julien Ryckaert:
STCO: Driving the More than Moore Era. ISVLSI 2024: 7-8 - [c29]Yukai Chen, Sankatali Venkateswarlu, Subrat Mishra, Julien Ryckaert, James Myers, Dwaipayan Biswas:
Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet. ISVLSI 2024: 45-50 - [c28]Aakash Patel, Dwaipayan Biswas, Joyjit Kundu, Yoojin Ban, Nicolas Pantano, Arindam Mallik, Julien Ryckaert, James Myers:
Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems. ISVLSI 2024: 118-123 - [c27]S. Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, Gioele Mirabelli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, D. Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert:
Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). VLSI Technology and Circuits 2024: 1-2 - 2023
- [c26]Carlos Escuin, Fernando García-Redondo
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS 2023: 1-5 - [c25]Subrat Mishra, Sankatali Venkateswarlu
Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). IRPS 2023: 1-7 - 2021
- [j12]Benoît Labbé
A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller. IEEE J. Solid State Circuits 56(2): 601-611 (2021) - 2020
- [c24]Pranay Prabhat, Benoît Labbé
27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power. ISSCC 2020: 422-424
2010 – 2019
- 2019
- [j11]Yunpeng Cai
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS. IEEE J. Solid State Circuits 54(2): 550-559 (2019) - [j10]Anand Savanth
A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator. IEEE J. Solid State Circuits 54(11): 3097-3106 (2019) - [c23]Philex Ming-Yan Fan, Anand Savanth
A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing. ESSCIRC 2019: 1-4 - [c22]Supreet Jeloka, Pranay Prabhat
A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy. ISLPED 2019: 1-6 - [i1]James Myers, Sebastian Karcher, Sebastian Ostrowski, Nic Weber:
Simple, Standards-based Archiving in Dataverse. RO 2019 - 2018
- [c21]Pranay Prabhat
A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup. A-SSCC 2018: 183-186 - [c20]Vivek De, Dennis Sylvester, James Myers, Jun Deguchi, Shinichiro Shiratake, Ingrid Verbauwhede
F1: Intelligent energy-efficient systems at the edge of IoT. ISSCC 2018: 502-504 - [c19]Jane S. Tsay, James Myers:
Communicative Efficiency in Child Mandarin. PACLIC 2018 - 2017
- [j9]Tatsuya Onuki
Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS. IEEE J. Solid State Circuits 52(4): 925-932 (2017) - [j8]Anand Savanth
Integrated Reciprocal Conversion With Selective Direct Operation for Energy Harvesting Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2370-2379 (2017) - [c18]Thomas Burd, James Myers, Byeong-Gyu Nam:
Session 3 overview: Digital processors. ISSCC 2017: 48-49 - [c17]Anand Savanth
5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability. ISSCC 2017: 96-97 - [c16]Jordan Morris, Pranay Prabhat
Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library. ISVLSI 2017: 19-24 - [c15]Yunpeng Cai, Anand Savanth
Evaluation and analysis of single-phase clock flip-flops for NTV applications. PATMOS 2017: 1-6 - [c14]Anand Savanth
A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems. VLSID 2017: 81-86 - 2016
- [j7]James Myers, Anand Savanth
A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator. IEEE J. Solid State Circuits 51(1): 31-44 (2016) - [c13]James Myers, Pranay Prabhat
Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem. PATMOS 2016: 56-63 - [c12]Tatsuya Onuki, Wataru Uesugi, Hikaru Tamura, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew, Chen Bin Lin, J. Y. Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki:
Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. VLSI Circuits 2016: 1-2 - 2015
- [c11]James Myers, Anand Savanth
8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications. ISSCC 2015: 1-3 - [c10]Anand Savanth, Alex S. Weddell, James Myers, David Flynn, Bashir M. Al-Hashimi:
Photovoltaic Cells for Micro-Scale Wireless Sensor Nodes: Measurement and Modeling to Assist System Design. ENSsys@SenSys 2015: 15-20 - 2014
- [j6]Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Wataru Uesugi, Atsuo Isobe, Naoaki Tsutsui, Yasutaka Suzuki, Yutaka Okazaki, Yukio Maehashi, Jun Koyama, Yoshitaka Yamamoto, Shunpei Yamazaki, Masahiro Fujita, James Myers, Pekka Korpinen:
Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor. IEEE Micro 34(6): 42-53 (2014) - [j5]Jatin N. Mistry, James Myers, Bashir M. Al-Hashimi, David Flynn, John Biggs, Geoff V. Merrett
Active Mode Subclock Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 1898-1908 (2014) - [c9]Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Tatsuya Onuki, Wataru Uesugi, Takuro Ohmaru, Kazuaki Ohshima
Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating. COOL Chips 2014: 1-3 - [c8]Jedrzej Kufel, Peter R. Wilson, Stephen Hill, Bashir M. Al-Hashimi, Paul N. Whatmough, James Myers:
Clock-modulation based watermark for protection of embedded processors. DATE 2014: 1-6 - 2013
- [c7]Yoshio Masubuchi, Bert Gyselinckx, Michael McCool, Shintaro Momose, James Myers, Toshio Yoshida:
Panel discussions the next step in processor evolution. COOL Chips 2013: 1-2 - [c6]Bert Gyselinckx, Hiroshi Kanayama, Michael McCool, Shintaro Momose, Takeshi Kataoka, James Myers, Toshio Yoshida:
Keynote & invited speaker's biography [7 biographies]. COOL Chips 2013: xxii-xxviii - 2012
- [j4]Jia-Cing Ruan, Chiung-Wen Hsu, James Myers, Jane S. Tsay:
Development and Testing of Transcription Software for a Southern Min Spoken Corpus. Int. J. Comput. Linguistics Chin. Lang. Process. 17(1) (2012) - [c5]James Myers:
Cognitive Styles in Two Cognitive Sciences. CogSci 2012 - [c4]Colin Wilson, Neil Cohn, James Myers, Stephen Goldberg, Ariel Cohen-Goldberg:
Grammatical Approaches to Written and Graphical Communication. CogSci 2012 - [c3]Jatin N. Mistry, John Biggs, James Myers, Bashir M. Al-Hashimi, David Flynn:
dRail: A Novel Physical Layout Methodology for Power Gated Circuits. PATMOS 2012: 245-255
2000 – 2009
- 2009
- [j3]James Myers
Lexical frequency effects in Taiwan Southern Min syllable contraction. J. Phonetics 37(2): 212-230 (2009) - [j2]James Myers
Syntactic Judgment Experiments. Lang. Linguistics Compass 3(1): 406-423 (2009) - 2007
- [j1]James Myers:
MiniJudge: Software for Small-Scale Experimental Syntax. Int. J. Comput. Linguistics Chin. Lang. Process. 12(2) (2007) - 2006
- [c2]James Myers:
MiniJudge: Software for minimalist experimental syntax. ROCLING 2006
1990 – 1999
- 1995
- [c1]James Myers, John Callahan:
Working group report on environments [program environments]. WETICE 1995: 5-7
Coauthor Index
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