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Lirida A. B. Naviner
Lírida A. B. Naviner – Lirida Alves de Barros Naviner
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- affiliation: Télécom Paris, Paris, France
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2020 – today
- 2024
- [j38]Esther Goudet
, Fabio Sureau, Paul Breuil, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche:
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach. J. Electron. Test. 40(3): 291-313 (2024) - 2023
- [j37]Hao Cai
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms. IEEE Des. Test 40(3): 17-25 (2023) - [c93]Esther Goudet, Luis Peña Treviño, Lirida A. B. Naviner
Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. LATS 2023: 1-6 - 2022
- [j36]David C. C. Freitas, Jarbas Silveira
OPCoSA: an Optimized Product Code for space applications. Integr. 84: 131-141 (2022) - [j35]Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner
Writing-only in-MRAM computing paradigm for ultra-low power applications. Microprocess. Microsystems 90: 104449 (2022) - [c92]Xuecan Yang, Sumanta Chaudhuri, Laurence Likforman, Lirida A. B. Naviner
Minconvnets: a New Class of Multiplication-Less Neural Networks. ICIP 2022: 881-885 - 2021
- [j34]Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner
A survey of in-spin transfer torque MRAM computing. Sci. China Inf. Sci. 64(6) (2021) - [c91]You-You Zhang, Lirida A. B. Naviner
Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM. ASICON 2021: 1-4 - [c90]Yaoru Hou
Cryogenic In-MRAM Computing. NANOARCH 2021: 1-6 - [c89]Yu-ang Wu, Lirida A. B. Naviner
Hybrid MTJ-CMOS Integration for Sigma-Delta ADC. NANOARCH 2021: 1-5 - [i2]Xuecan Yang, Sumanta Chaudhuri, Laurence Likforman, Lirida A. B. Naviner
MinConvNets: A new class of multiplication-less Neural Networks. CoRR abs/2101.09492 (2021) - 2020
- [j33]Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner
Magnetic Tunnel Junction Applications. Sensors 20(1): 121 (2020) - [c88]Nilson Maciel, Elaine Crespo Marques, Lírida A. B. Naviner
Magnetic Tunnel Junction-based Analog-to-Digital Converter using Spin Orbit Torque Mechanism. ICECS 2020: 1-4 - [c87]Xuecan Yang, Sumanta Chaudhuri, Lirida A. B. Naviner
Quad-Approx CNNs for Embedded Object Detection Systems. ICECS 2020: 1-4
2010 – 2019
- 2019
- [j32]Elaine Crespo Marques
A Review of Sparse Recovery Algorithms. IEEE Access 7: 1300-1322 (2019) - [j31]Francisco Veirano, Lirida A. B. Naviner
Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI. Integr. 65: 211-218 (2019) - [j30]Hao Cai
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 239-250 (2019) - [c86]Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner
Deep Learning Approaches for Sparse Recovery in Compressive Sensing. ISPA 2019: 129-134 - [c85]Mingyue Liu, Hao Cai, Menglin Han, Lei Xie, Jun Yang, Lirida A. B. Naviner
Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM. NANOARCH 2019: 1-6 - [c84]Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner
Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery. SiPS 2019: 324-329 - 2018
- [j29]Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner
Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology. Microelectron. Reliab. 88-90: 965-968 (2018) - [c83]Menglin Han, Hao Cai, Jun Yang, Lirida A. B. Naviner
Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement. APCCAS 2018: 386-389 - [c82]Hao Cai, Menglin Han, You Wang, Lirida A. B. Naviner
Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. DCIS 2018: 1-5 - [c81]You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, Lirida A. B. Naviner
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning. ACM Great Lakes Symposium on VLSI 2018: 403-408 - [c80]Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner
Compressed Sensing for Wideband HF Channel Estimation. ICFSP 2018: 1-5 - [c79]Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner
Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. ISCAS 2018: 1-5 - [c78]Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner
MRAM-on-FDSOI Integration: A Bit-Cell Perspective. ISVLSI 2018: 263-268 - [c77]Rafael B. Schvittz, Matheus F. Pontes, Cristina Meinhardt
Reliability evaluation of circuits designed in multi- and single-stage versions. LASCAS 2018: 1-4 - [c76]Fábio B. Armelin, Lírida A. B. Naviner
Using FPGA self-produced transients to emulate SETs for SER estimation. LATS 2018: 1-3 - [c75]Fábio B. Armelin, Lirida A. B. Naviner
Probability aware fault-injection approach for SER estimation. LATS 2018: 1-3 - [c74]Tian Ban, Baokun Wang, Lirida A. B. Naviner
Design, Synthesis and Application of A Novel Approximate Adder. MWSCAS 2018: 488-491 - 2017
- [j28]Mariem Slimani
Analysis of ageing effects on ARTIX7 XILINX FPGA. Microelectron. Reliab. 76-77: 168-173 (2017) - [j27]Hao Cai, You Wang, Lirida Alves de Barros Naviner
Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 847-857 (2017) - [j26]Francisco Veirano
Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(12): 3081-3091 (2017) - [c73]Hao Cai, You Wang, Lirida A. B. Naviner
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device. ACM Great Lakes Symposium on VLSI 2017: 23-28 - [c72]Nilson Maciel de Paiva, Elaine Crespo Marques, Lirida Alves de Barros Naviner
Sparsity analysis using a mixed approach with greedy and LS algorithms on channel estimation. ICFSP 2017: 91-95 - [c71]Hao Cai, You Wang, Lirida A. B. Naviner
Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. ISVLSI 2017: 57-61 - [c70]Francisco Veirano, Fernando Silveira, Lirida A. B. Naviner
Asymmetrical length biasing for energy efficient digital circuits. LASCAS 2017: 1-4 - 2016
- [j25]Francisco Veirano, Fernando Silveira, Lirida A. B. Naviner
Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS. J. Low Power Electron. 12(1): 74-81 (2016) - [j24]Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner
Efficient reliability evaluation methodologies for combinational circuits. Microelectron. Reliab. 64: 19-25 (2016) - [j23]You Wang, Hao Cai, Lirida A. B. Naviner
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI. Microelectron. Reliab. 64: 26-30 (2016) - [j22]Mariem Slimani, Paulo F. Butzen
Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters. Microelectron. Reliab. 64: 48-53 (2016) - [c69]Fábio B. Armelin, Lírida A. B. Naviner
Impact evaluation of logic blocks configuration on FPGA's soft error rate estimation. ICECS 2016: 277-280 - [c68]Nenad Jovanovic, Olivier Thomas, Elisa Vianello, Bosko Nikolic, Lirida A. B. Naviner
Design considerations for reliable OxRAM-based non-volatile flip-flops in 28nm FD-SOI technology. ISCAS 2016: 1146-1149 - [c67]You Wang, Hao Cai, Lirida A. B. Naviner
A novel circuit design of true random number generator using magnetic tunnel junction. NANOARCH 2016: 123-128 - [c66]Hao Cai, You Wang, Lirida A. B. Naviner
Approximate computing in MOS/spintronic non-volatile full-adder. NANOARCH 2016: 203-208 - [c65]Francisco Veirano, Lirida A. B. Naviner
Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. PATMOS 2016: 243-249 - [c64]Rafael B. Schivittz, Rafael Fritz, Denis Teixeira Franco, Lirida A. B. Naviner
Inserting permanent fault input dependence on PTM to improve robustness evaluation. SBCCI 2016: 1-6 - 2015
- [j21]Hao Cai, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner
Cross-layer investigation of continuous-time sigma-delta modulator under aging effects. Microelectron. Reliab. 55(3-4): 645-653 (2015) - [j20]Arwa Ben Dhia, Mariem Slimani, Hao Cai, Lirida A. B. Naviner:
A dual-rail compact defect-tolerant multiplexer. Microelectron. Reliab. 55(3-4): 662-670 (2015) - [j19]Ting An, Kaikai Liu, Hao Cai, Lirida A. B. Naviner:
Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method. Microelectron. Reliab. 55(3-4): 696-703 (2015) - [j18]Mariem Slimani
A novel analytical method for defect tolerance assessment. Microelectron. Reliab. 55(9-10): 1285-1289 (2015) - [j17]Hao Cai, You Wang, Lirida A. B. Naviner
Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology. Microelectron. Reliab. 55(9-10): 1323-1327 (2015) - [j16]Y. Wang, Hao Cai, Lirida A. B. Naviner
Compact thermal modeling of spin transfer torque magnetic tunnel junction. Microelectron. Reliab. 55(9-10): 1649-1653 (2015) - [c63]Mariem Slimani, Lirida A. B. Naviner
A tool for transient fault analysis in combinational circuits. ICECS 2015: 125-128 - [c62]Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Gilles Gasiot, Fady Abouzeid
Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. IRPS 2015: 12 - [c61]Xavier Pons, Christophe Gruet, Eric Georgeaux, Lirida A. B. Naviner
An energy efficient D2D LTE structure for PMR based on FlashLinQ. ISWCS 2015: 11-15 - [c60]Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Lirida A. B. Naviner
Partial triplication of a SPARC-V8 microprocessor using fault injection. LASCAS 2015: 1-4 - [c59]Lirida Alves de Barros Naviner
Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction. NEWCAS 2015: 1-4 - [c58]Xavier Pons Masbernat, Christophe Gruet, Eric Georgeaux, Lirida A. B. Naviner
D2D broadcast communications for 4G PMR networks. NTMS 2015: 1-5 - 2014
- [j15]You Wang, Yue Zhang, Erya Deng, Jacques-Olivier Klein
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses. Microelectron. Reliab. 54(9-10): 1774-1778 (2014) - [c57]Xavier Pons Masbernat, Saud Althunibat, Godfrey Kibalya
Battery-aware network discovery algorithm for mobile terminals within heterogeneous networks. CAMAD 2014: 1-5 - [c56]Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner
Shadow-scan design with low latency overhead and in-situ slack-time monitoring. ETS 2014: 1-6 - [c55]Xavier Pons Masbernat, Agapi Mesodiakaki, Christophe Gruet, Lirida A. B. Naviner
An energy efficient vertical handover decision algorithm. GLOBECOM Workshops 2014: 1145-1150 - [c54]Lirida A. B. Naviner
Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. ICICDT 2014: 1-4 - [c53]Mariem Slimani, Arwa Ben Dhia, Lirida A. B. Naviner
Cross logic: A new approach for defect-tolerant circuits. ICICDT 2014: 1-4 - [c52]Arwa Ben Dhia, Mariem Slimani, Lirida A. B. Naviner
Comparative study of defect-tolerant multiplexers for FPGAs. IOLTS 2014: 7-12 - [c51]Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner
Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. IOLTS 2014: 160-163 - [c50]Samuel N. Pagliarini
A hybrid reliability assessment method and its support of sequential logic modelling. IOLTS 2014: 182-183 - [c49]Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI 2014: 553-558 - [c48]Arwa Ben Dhia, Mariem Slimani, Lirida A. B. Naviner
Improving the robustness of a switch box in a mesh of clusters FPGA. LATW 2014: 1-6 - [c47]Ting An, Hao Cai, Lirida Alves de Barros Naviner
Simulation study of aging in CMOS binary adders. MIPRO 2014: 51-55 - [c46]Ting An, Kaikai Liu, Lirida Alves de Barros Naviner
Analytical method for reliability assessment of concurrent checking circuits under multiple faults. MIPRO 2014: 56-59 - [c45]Arwa Ben Dhia, Mariem Slimani, Lirida A. B. Naviner
A defect-tolerant multiplexer using differential logic for FPGAs. MIXDES 2014: 375-380 - [c44]Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner
Reliability-aware delay faults evaluation of CMOS flip-flops. MIXDES 2014: 385-389 - [c43]Ting An, Kaikai Liu, Hao Cai, Lirida Alves de Barros Naviner
Efficient implementation for accurate analysis of CED circuits against multiple faults. MIXDES 2014: 436-440 - [c42]Lirida Alves de Barros Naviner
Analytical methods to assess transient faults effects in logic circuits. MWSCAS 2014: 667-670 - [c41]Nenad Jovanovic, Olivier Thomas, Elisa Vianello, Jean-Michel Portal, Bosko Nikolic, Lirida A. B. Naviner
OxRAM-based non volatile flip-flop in 28nm FDSOI. NEWCAS 2014: 141-144 - 2013
- [j14]Arwa Ben Dhia, Samuel N. Pagliarini
A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. Microelectron. Reliab. 53(9-11): 1189-1193 (2013) - [j13]Samuel N. Pagliarini
SNaP: A novel hybrid method for circuit reliability assessment under multiple faults. Microelectron. Reliab. 53(9-11): 1230-1234 (2013) - [c40]Xavier Pons Masbernat, Raúl Palacios, Christophe Gruet, Lirida A. B. Naviner
Uplink energy efficiency in LTE systems. CAMAD 2013: 109-113 - [c39]Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. DATE 2013: 1077-1082 - [c38]Arwa Ben Dhia, Lirida A. B. Naviner
Evaluating CLB designs under multiple SETs in SRAM-based FPGAs. DFTS 2013: 112-117 - [c37]Ting An, Lirida Alves de Barros Naviner
A low cost reliable architecture for S-Boxes in AES processors. DFTS 2013: 155-160 - [c36]Kaikai Liu, Hao Cai, Ting An, Lirida A. B. Naviner
Reliability analysis of combinational circuits with the influences of noise and single-event transients. DFTS 2013: 218-223 - [c35]Kaikai Liu, Ting An, Hao Cai, Lirida A. B. Naviner
A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology. EUROCON 2013: 1829-1836 - [c34]Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner
A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT 2013: 434-437 - [c33]Samuel N. Pagliarini
Single event transient mitigation through pulse quenching: Effectiveness at circuit level. ICECS 2013: 121-124 - [c32]Arwa Ben Dhia, Lirida A. B. Naviner
Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs. LATW 2013: 1-6 - [c31]Samuel N. Pagliarini
Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis. MWSCAS 2013: 113-116 - [c30]Tian Ban, Jianxin Wang, Ting An, Lirida A. B. Naviner
Modeling of transient faults and fault-tolerant design in nanoelectronics. MWSCAS 2013: 545-548 - [c29]Ting An, Lirida Alves de Barros Naviner
Evaluation of fault-tolerant composite field AES S-boxes under multiple transient faults. NEWCAS 2013: 1-4 - [c28]Samuel N. Pagliarini
Selective hardening against multiple faults employing a net-based reliability analysis. NEWCAS 2013: 1-4 - 2012
- [j12]Samuel N. Pagliarini
Exploring the feasibility of selective hardening for combinational logic. Microelectron. Reliab. 52(9-10): 1843-1847 (2012) - [c27]Xavier Pons Masbernat, Christophe Gruet, Frédéric Fraysse, Serge Contal, Lirida A. B. Naviner
Green solutions for future LTE PMR networks. CAMAD 2012: 165-167 - [c26]Matteo Causo, Ting An, Lirida Alves de Barros Naviner
Parallel scaling-free and area-time efficient CORDIC algorithm. ICECS 2012: 149-152 - [c25]Samuel N. Pagliarini
Automatic selective hardening against soft errors: A cost-based and regularity-aware approach. ICECS 2012: 753-756 - [c24]Ting An, Matteo Causo, Lirida Alves de Barros Naviner
Transient fault analysis of CORDIC processor. ICECS 2012: 757-760 - [c23]Arwa Ben Dhia, Lirida Alves de Barros Naviner
A new fault-tolerant architecture for CLBs in SRAM-based FPGAs. ICECS 2012: 761-764 - [c22]Arwa Ben Dhia, Lirida A. B. Naviner
Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster. IOLTS 2012: 31-36 - [c21]Samuel Nascimento Pagliarini
Selective hardening methodology for combinational logic. LATW 2012: 1-6 - [c20]Kaikai Liu, Tian Ban, Lirida A. B. Naviner
Reliability analysis of a Reed-Solomon decoder. MWSCAS 2012: 438-441 - [c19]Tian Ban, Lirida Alves de Barros Naviner
Majority voter: Signal probability, reliability and error bound characteristics. MWSCAS 2012: 538-541 - 2011
- [j11]Lirida A. B. Naviner
FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level. Microelectron. Reliab. 51(9-11): 1459-1463 (2011) - [j10]Tian Ban, Lirida A. B. Naviner
Progressive module redundancy for fault-tolerant designs in nanoelectronics. Microelectron. Reliab. 51(9-11): 1489-1492 (2011) - [c18]Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner
An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. IOLTS 2011: 98-103 - 2010
- [j9]Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner
Fast reliability analysis of combinatorial logic circuits using conditional probabilities. Microelectron. Reliab. 50(9-11): 1215-1218 (2010) - [j8]G. G. dos Santos, Elaine Crespo Marques, Lirida A. B. Naviner
Using error tolerance of target application for efficient reliability improvement of digital circuits. Microelectron. Reliab. 50(9-11): 1219-1222 (2010) - [j7]Elaine Crespo Marques, Lirida A. B. Naviner
An efficient tool for reliability improvement based on TMR. Microelectron. Reliab. 50(9-11): 1247-1250 (2010) - [c17]Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner
Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. ICECS 2010: 263-267 - [c16]Hicham Ezzat, Lirida A. B. Naviner
Level matrix propagation for reliability analysis of nano-scale circuits based on probabilistic transfer matrix. ISQED 2010: 524-527 - [c15]Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner
On evaluating the signal reliability of self-checking arithmetic circuits. SBCCI 2010: 109-114
2000 – 2009
- 2009
- [c14]Ali Beydoun, Van Tam Nguyen, Lirida A. B. Naviner
A 65 nm CMOS Digital Processor for Multi-mode Time Interleaved High-pass SigmaDelta A/D Converters. ISCAS 2009: 1561-1564 - 2008
- [j6]Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner
Signal probability for reliability evaluation of logic circuits. Microelectron. Reliab. 48(8-9): 1586-1591 (2008) - [j5]Maí Correia R. de Vasconcelos, Denis Teixeira Franco, Lirida A. B. Naviner
Relevant metrics for evaluation of concurrent error detection schemes. Microelectron. Reliab. 48(8-9): 1601-1603 (2008) - [c13]Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner
Reliability analysis of logic circuits based on signal probability. ICECS 2008: 670-673 - [c12]Maí Correia R. de Vasconcelos, Denis Teixeira Franco, Lirida A. B. Naviner
On the output events in concurrent error detection schemes. ICECS 2008: 978-981 - [i1]Lirida Alves de Barros Naviner, Jean-François Naviner, Denis Teixeira Franco, Maí Correia R. de Vasconcelos:
Methods and Metrics for Reliability Assessment. Fault-Tolerant Distributed Algorithms on VLSI Chips 2008 - 2006
- [j4]Denis Teixeira Franco, Jean-François Naviner
Yield and reliability issues in nanoelectronic technologies. Ann. des Télécommunications 61(11-12): 1422-1457 (2006) - [j3]Ioannis Krikidis
An iterative reconfigurability approach for WCDMA high-data-rate communications. IEEE Wirel. Commun. 13(3): 8-14 (2006) - 2005
- [c11]Khaled Grati, Adel Ghazel, Lirida A. B. Naviner
Design and hardware implementation of digital channel selection decimating filter for multistandard receiver. ICECS 2005: 1-4 - [c10]Daniel C. de Souza, Ioannis Krikidis
Heterogeneous implementation of a rake receiver for DS-CDMA communication systems. ICECS 2005: 1-4 - [c9]Ioannis Krikidis, Jean-Luc Danger, Lirida A. B. Naviner:
Reconfigurable Implementation Issues of a Detection Scheme for DS-CDMA High Data Rate Connections. PIMRC 2005: 695-699 - 2004
- [c8]Ioannis Krikidis, Jean-Luc Danger, Lirida A. B. Naviner:
A finger configuration algorithm for a reconfigurable Rake receiver. WCNC 2004: 311-315 - 2003
- [c7]Elizabeth Colin
On baseband considerations for multistandard RF receivers. ICECS 2003: 691-694 - [c6]Zouhair M. Belkoura, Lirida A. B. Naviner
Hardware implementation issues of a BMS decoding approach for AG based codes. WCNC 2003: 448-453 - 2002
- [j2]Patrick Loumeau, Jean-François Naviner, Hervé Petit, Lirida A. B. Naviner, Patricia Desgreys:
Analog to digital conversion: technical aspects. Ann. des Télécommunications 57(5-6): 338-385 (2002) - [j1]Adel Ghazel, Lirida A. B. Naviner
On design and implementation of a decimation filter for multistandard wireless transceivers. IEEE Trans. Wirel. Commun. 1(4): 558-562 (2002) - [c5]Khaled Grati, Adel Ghazel, Lirida A. B. Naviner
Relaxed decimation filter specifications for wireless transceivers. ICECS 2002: 565-569 - 2001
- [c4]Elizabeth Colin
Antialiasing filtering influences on ADC specifications for radio receivers. ICECS 2001: 1469-1472 - [c3]Khaled Grati, Adel Ghazel, Lirida A. B. Naviner, Faker Moatamri:
Design and implementation of cascade decimation filter for radio communications. ICECS 2001: 1603-1606 - [c2]Elizabeth Colin
Trade-off between antialiasing filter and analog-to-digital converters specifications in homodyne radio frequency receivers. VTC Fall 2001: 2351-2354
1990 – 1999
- 1999
- [c1]Lirida A. B. Naviner, Jean-Luc Danger, C. Laurent:
High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA. FPGA 1999: 249
Coauthor Index
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