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Baris Taskin
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- affiliation: Drexel University
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2020 – today
- 2024
- [c90]Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin:
Design Automation for Charge Recovery Logic. ISCAS 2024: 1-5 - [c89]Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin:
High-Speed Phase-Based Computing. ISCAS 2024: 1-5 - 2022
- [j32]Amlan Ganguly
, Sergi Abadal
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion. IEEE Micro 42(3): 40-49 (2022) - [j31]Ragh Kuttappa
Multiphase Digital Low-Dropout Regulators. IEEE Trans. Very Large Scale Integr. Syst. 30(1): 40-50 (2022) - [c88]Ragh Kuttappa, Baris Taskin:
A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators. ISCAS 2022: 687-691 - [c87]Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, Anuradha Srinivasan:
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. ISCAS 2022: 692-696 - 2021
- [j30]Ragh Kuttappa
Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1636-1645 (2021) - [c86]Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin:
Scalable Resonant Power Clock Generation for Adiabatic Logic Design. ISVLSI 2021: 338-342 - 2020
- [j29]Vasil Pano
TSV Antennas for Multi-Band Wireless Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(1): 100-113 (2020) - [c85]Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, Mark Hempstead:
SnackNoC: Processing in the Communication Layer. HPCA 2020: 461-473 - [c84]Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, Baris Taskin:
Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking. ISCAS 2020: 1-5 - [c83]Ragh Kuttappa, Baris Taskin:
FinFET - Based Low Swing Rotary Traveling Wave Oscillators. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j28]Ragh Kuttappa
RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2685-2698 (2019) - [j27]Leo Filippini
The Adiabatically Driven StrongARM Comparator. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1957-1961 (2019) - [j26]Ragh Kuttappa
FOPAC: Flexible On-Chip Power and Clock. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4628-4636 (2019) - [j25]Scott Lerner
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 1-10 (2019) - [j24]Scott Lerner
Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 700-710 (2019) - [j23]Weicheng Liu, Can Sitik
SLECTS: Slew-Driven Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 864-874 (2019) - [c82]Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman:
Low Voltage Clock Tree Synthesis with Local Gate Clusters. ACM Great Lakes Symposium on VLSI 2019: 99-104 - [c81]Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin:
Low Swing - Low Frequency Rotary Traveling Wave Oscillators. ISCAS 2019: 1-5 - [c80]Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis:
Robust Low Power Clock Synchronization for Multi-Die Systems. ISLPED 2019: 1-6 - [c79]Baris Taskin:
On-chip wireless interconnect paradigm. NoCArc@MICRO 2019: 1:1 - [c78]Vasil Pano, Ragh Kuttappa, Baris Taskin:
3D NoCs with active interposer for multi-die systems. NOCS 2019: 14:1-14:8 - [c77]Longfei Wang, Ragh Kuttappa, Baris Taskin, Selçuk Köse
Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation. SLIP 2019: 1-5 - [e3]Houman Homayoun, Baris Taskin, Tinoosh Mohsenin, Weisheng Zhao:
Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019. ACM 2019, ISBN 978-1-4503-6252-8 [contents] - 2018
- [j22]Karthik Sangaiah, Michael Lui, Radhika Jagtap, Stephan Diestelhorst, Siddharth Nilakantan, Ankit More, Baris Taskin, Mark Hempstead:
SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads. ACM Trans. Archit. Code Optim. 15(1): 2:1-2:26 (2018) - [j21]Ankit More, Vasil Pano
Vertical Arbitration-Free 3-D NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1853-1866 (2018) - [c76]Scott Lerner, Baris Taskin:
Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis. IGSC 2018: 1-6 - [c75]Leo Filippini
A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion. ISCAS 2018: 1-5 - [c74]Ragh Kuttappa, Baris Taskin:
Low Frequency Rotary Traveling Wave Oscillators. ISCAS 2018: 1-5 - [c73]Scott Lerner, Vasil Pano, Baris Taskin:
NoC Router Lifetime Improvement using Per-Port Router Utilization. ISCAS 2018: 1-5 - [c72]Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, Baris Taskin:
Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement. ISCAS 2018: 1-5 - [c71]Michael Lui, Karthik Sangaiah, Mark Hempstead, Baris Taskin:
Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces. ISPASS 2018: 169-178 - [e2]Deming Chen, Houman Homayoun, Baris Taskin:
Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018. ACM 2018 [contents] - 2017
- [j20]Tsung-Yi Ho
Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016. Integr. 58: 225 (2017) - [c70]Ragh Kuttappa, Lunal Khuon, Bahram Nabet, Baris Taskin:
Reconfigurable threshold logic gates using optoelectronic capacitors. DATE 2017: 614-617 - [c69]Ragh Kuttappa, Leo Filippini
Stability of Rotary Traveling Wave Oscillators under process variations and NBTI. ISCAS 2017: 1-4 - [c68]Leo Filippini
Wireless charge recovery system for implanted electroencephalography applications in mice. ISQED 2017: 342-345 - [c67]Scott Lerner, Baris Taskin:
Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors. ISQED 2017: 379-384 - [c66]Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin, Kapil R. Dandekar
Wireless NoCs Using Directional and Substrate Propagation Antennas. ISVLSI 2017: 188-193 - [c65]Scott Lerner, Baris Taskin:
WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS. ISVLSI 2017: 465-470 - [c64]Leo Filippini
Charge recovery implementation of an analog comparator: Initial results. MWSCAS 2017: 1505-1508 - [c63]Leo Filippini
A charge recovery logic system bus. SLIP 2017: 1-4 - [c62]Scott Lerner, Eric Leggett, Baris Taskin:
Slew-down: analysis of slew relaxation for low-impact clock buffers. SLIP 2017: 1-4 - 2016
- [j19]Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman:
Design Methodology for Voltage-Scaled Clock Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3080-3093 (2016) - [c61]Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin, Kapil R. Dandekar
Wireless Network-on-Chip analysis of propagation technique for on-chip communication. ICCD 2016: 400-403 - [c60]Vasil Pano, Isikcan Yilmaz, Ankit More, Baris Taskin:
Energy aware routing of multi-level Network-on-Chip traffic. ICCD 2016: 480-486 - [c59]Leo Filippini
Charge recovery logic for thermal harvesting applications. ISCAS 2016: 542-545 - [c58]Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
Exploiting useful skew in gated low voltage clock trees. ISCAS 2016: 2595-2598 - [e1]Baris Taskin, Tsung-Yi Ho
Proceedings of the 18th System Level Interconnect Prediction Workshop, SLIP 2016, Austin, TX, USA, June 4, 2016. ACM 2016, ISBN 978-1-4503-4430-2 [contents] - 2015
- [j18]Can Sitik, Emre Salman, Leo Filippini
FinFET-Based Low-Swing Clocking. ACM J. Emerg. Technol. Comput. Syst. 12(2): 13:1-13:20 (2015) - [j17]Ankit More, Baris Taskin:
Locality-Aware Network Utilization Balancing in NoCs. ACM Trans. Design Autom. Electr. Syst. 21(1): 6:1-6:26 (2015) - [j16]Ying Teng, Baris Taskin:
ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2519-2530 (2015) - [c57]Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks. ACM Great Lakes Symposium on VLSI 2015: 283-288 - [c56]Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
A Novel Static D-Flip-Flop Topology for Low Swing Clocking. ACM Great Lakes Symposium on VLSI 2015: 301-306 - [c55]Karthik Sangaiah, Mark Hempstead, Baris Taskin:
Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling. ICCAD 2015: 365-372 - [c54]Leo Filippini
A wirelessly powered system with charge recovery logic. ICCD 2015: 505-510 - [c53]Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
Enhanced level shifter for multi-voltage operation. ISCAS 2015: 1442-1445 - [c52]Siddharth Nilakantan
Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation. ISPASS 2015: 278-287 - [c51]Giordano Salvador, Siddharth Nilakantan
Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping. VLSID 2015: 129-134 - [c50]Siddharth Nilakantan
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation. VLSID 2015: 135-140 - 2014
- [j15]Can Sitik, Baris Taskin
Iterative skew minimization for low swing clocks. Integr. 47(3): 356-364 (2014) - [c49]Ying Teng, Baris Taskin:
Frequency-centric resonant rotary clock distribution network design. ICCAD 2014: 742-749 - [c48]Can Sitik, Scott Lerner, Baris Taskin:
Timing characterization of clock buffers for clock tree synthesis. ICCD 2014: 230-236 - [c47]Giordano Salvador, Siddharth Nilakantan
Static thread mapping for NoCs via binary instrumentation traces. ICCD 2014: 517-520 - [c46]Can Sitik, Leo Filippini
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design. ISVLSI 2014: 498-503 - [c45]Julian Kemmerer, Baris Taskin:
Range-based dynamic routing of hierarchical on chip network traffic. SLIP 2014: 5:1-5:9 - 2013
- [c44]Ying Teng, Baris Taskin:
Sparse-rotary oscillator array (SROA) design for power and skew reduction. DATE 2013: 1229-1234 - [c43]Can Sitik, Baris Taskin:
Skew-bounded low swing clock tree optimization. ACM Great Lakes Symposium on VLSI 2013: 49-54 - [c42]Can Sitik, Baris Taskin:
Multi-corner multi-voltage domain clock mesh design. ACM Great Lakes Symposium on VLSI 2013: 209-214 - [c41]Ying Teng, Baris Taskin:
Rotary traveling wave oscillator frequency division at nanoscale technologies. ACM Great Lakes Symposium on VLSI 2013: 349-350 - [c40]Ying Teng, Baris Taskin:
Resonant frequency divider design methodology for dynamic frequency scaling. ICCD 2013: 479-482 - [c39]Can Sitik, Prawat Nagvajara, Baris Taskin:
A microcontroller-based embedded system design course with PSoC3. MSE 2013: 28-31 - [c38]Baris Taskin:
Wireless on Networks-on-Chip. SLIP 2013: 1-2 - 2012
- [j14]Jianchao Lu, Xiaomi Mao, Baris Taskin:
Integrated Clock Mesh Synthesis With Incremental Register Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 217-227 (2012) - [j13]Jianchao Lu, Ying Teng, Baris Taskin:
A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1002-1011 (2012) - [j12]Vinayak Honkote, Baris Taskin:
ZeROA: Zero Clock Skew Rotary Oscillatory Array. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1528-1532 (2012) - [c37]Ying Teng, Baris Taskin:
Synchronization scheme for brick-based rotary oscillator arrays. ACM Great Lakes Symposium on VLSI 2012: 117-122 - [c36]Jianchao Lu, Xiaomi Mao, Baris Taskin:
Clock mesh synthesis with gated local trees and activity driven register clustering. ICCAD 2012: 691-697 - [c35]Matthew R. Guthaus, Baris Taskin:
High-Performance, Low-Power Resonant Clocking: Embedded tutorial. ICCAD 2012: 742-745 - [c34]Ying Teng, Baris Taskin:
Clock mesh synthesis method using the Earth Mover's Distance under transformations. ICCD 2012: 121-126 - [c33]Can Sitik, Baris Taskin:
Multi-voltage domain clock mesh design. ICCD 2012: 201-206 - [c32]Ankit More, Baris Taskin:
A unified design methodology for a hybrid wireless 2-D NoC. ISCAS 2012: 640-643 - [c31]Ankit More, Baris Taskin:
A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs. SLIP 2012: 22 - [c30]Vinayak Honkote, Ankit More, Baris Taskin:
3-D Parasitic Modeling for Rotary Interconnects. VLSI Design 2012: 137-142 - 2011
- [j11]Shannon M. Kurtas, Baris Taskin:
Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling. J. Circuits Syst. Comput. 20(5): 881-898 (2011) - [j10]Jianchao Lu, Baris Taskin:
Clock buffer polarity assignment with skew tuning. ACM Trans. Design Autom. Electr. Syst. 16(4): 49:1-49:22 (2011) - [j9]Vinayak Honkote, Baris Taskin:
CROA: Design and Analysis of the Custom Rotary Oscillatory Array. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1837-1847 (2011) - [c29]Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin:
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing. DATE 2011: 455-460 - [c28]Ankit More, Baris Taskin:
EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs. ICCD 2011: 19-24 - [c27]Ying Teng, Jianchao Lu, Baris Taskin:
ROA-brick topology for rotary resonant clocks. ICCD 2011: 273-278 - [c26]Jianchao Lu, Yusuf Aksehir, Baris Taskin:
Register On MEsh (ROME): A novel approach for clock mesh network synthesis. ISCAS 2011: 1219-1222 - [c25]Jianchao Lu, Baris Taskin:
Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits. ISCAS 2011: 1940-1943 - [c24]Jianchao Lu, Xiaomi Mao, Baris Taskin:
Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis. ISPD 2011: 131-138 - [c23]Ying Teng, Baris Taskin:
Process variation sensitivity of the Rotary Traveling Wave Oscillator. ISQED 2011: 236-242 - [c22]Jianchao Lu, Baris Taskin:
From RTL to GDSII: An ASIC design course development using Synopsys® University Program. MSE 2011: 72-75 - [c21]Ankit More, Baris Taskin:
Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip. SLIP 2011: 1 - 2010
- [j8]Ying Teng, Baris Taskin:
Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect. J. Low Power Electron. 6(4): 491-502 (2010) - [j7]Jianchao Lu, Baris Taskin
Post-CTS Delay Insertion. VLSI Design 2010: 451809:1-451809:9 (2010) - [c20]Ankit More, Baris Taskin:
Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects. ACM Great Lakes Symposium on VLSI 2010: 413-416 - [c19]Vinayak Honkote, Baris Taskin:
Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array. ICCD 2010: 209-214 - [c18]Vinayak Honkote, Baris Taskin:
PEEC based parasitic modeling for power analysis on custom rotary rings. ISLPED 2010: 111-116 - [c17]Ankit More, Baris Taskin:
Leakage current analysis for intra-chip wireless interconnects. ISQED 2010: 49-53 - [c16]Vinayak Honkote, Baris Taskin:
Skew analysis and bounded skew constraint methodology for rotary clocking technology. ISQED 2010: 413-417 - [c15]Jianchao Lu, Baris Taskin:
Clock buffer polarity assignment considering capacitive load. ISQED 2010: 765-770 - [c14]Jianchao Lu, Baris Taskin:
Clock Tree Synthesis with XOR Gates for Polarity Assignment. ISVLSI 2010: 17-22 - [c13]Ankit More, Baris Taskin:
Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs. ISVLSI 2010: 228-231 - [c12]Ankit More, Baris Taskin:
Simulation based study of wireless RF interconnects for practical CMOs implementation. SLIP 2010: 35-42 - [c11]Ankit More, Baris Taskin:
Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC. SoCC 2010: 447-452 - [c10]Vinayak Honkote, Baris Taskin:
Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. VLSI Design 2010: 218-223
2000 – 2009
- 2009
- [j6]Baris Taskin, Ivan S. Kourtev:
Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits. J. Circuits Syst. Comput. 18(5): 899-908 (2009) - [j5]Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo:
A shift-register-based QCA memory architecture. ACM J. Emerg. Technol. Comput. Syst. 5(1): 4:1-4:18 (2009) - [j4]Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner:
Custom topology rotary clock router with tree subnetworks. ACM Trans. Design Autom. Electr. Syst. 14(3): 44:1-44:14 (2009) - [c9]Vinayak Honkote, Baris Taskin:
Zero clock skew synchronization with rotary clocking technology. ISQED 2009: 588-593 - 2008
- [j3]Baris Taskin, Bo Hong:
Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1648-1656 (2008) - [c8]Vinayak Honkote, Baris Taskin:
Custom rotary clock router. ICCD 2008: 114-119 - 2007
- [c7]Prawat Nagvajara, Baris Taskin:
Design-for-Debug: A Vital Aspect in Education. MSE 2007: 65-66 - [c6]Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo:
A shift-register-based QCA memory architecture. NANOARCH 2007: 54-61 - 2006
- [j2]Baris Taskin, Ivan S. Kourtev:
Delay Insertion Method in Clock Skew Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 651-663 (2006) - 2005
- [c5]Baris Taskin, Ivan S. Kourtev:
Delay insertion method in clock skew scheduling. ISPD 2005: 47-54 - 2004
- [j1]Baris Taskin, Ivan S. Kourtev:
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 12-27 (2004) - [c4]Baris Taskin, Ivan S. Kourtev:
Advanced timing of level-sensitive sequential circuits. ICECS 2004: 603-606 - [c3]Baris Taskin, Ivan S. Kourtev:
Performance improvement of edge-triggered sequential circuits. ICECS 2004: 607-610 - [c2]Baris Taskin, Ivan S. Kourtev:
Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. ISCAS (2) 2004: 617-620 - 2002
- [c1]Baris Taskin, Ivan S. Kourtev:
Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 111-118
Coauthor Index
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