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ICCAD 2008: San Jose, California, USA
- Sani R. Nassif, Jaijeet S. Roychowdhury:
2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008. IEEE Computer Society 2008, ISBN 978-1-4244-2820-5
Keynotes
- Mary Lou Jepsen:
CAD for displays! 1 - Dmitri "Mitya" Chklovskii:
What can brain researchers learn from computer engineers and vice versa? 2
Tutorials
- Subhasish Mitra, Ravishankar K. Iyer, Kishor S. Trivedi, James W. Tschanz:
Reliable system design: models, metrics and design techniques. 3 - Joel R. Phillips, Kurt Keutzer, Michael Wrinn:
Architecting parallel programs. 4 - Chao Wang, Malay K. Ganai, Shuvendu K. Lahiri, Daniel Kroening
:
Embedded software verification: challenges and solutions. 5 - David Z. Pan, Stephen Renwick, Vivek Singh, Judy Huckabay:
Nanolithography and CAD challenges for 32nm/22nm and beyond. 6
Designer's panel
- Dan Bailey, Eric Soenen, Puneet Gupta, Paul G. Villarrubia, Sang H. Dhong:
Challenges at 45nm and beyond. 7 - Henry Chang, William Walker, John G. Maneatis, John F. Croix:
Mixed-signal simulation challenges and solutions. 8
Panel
- Rob Aitken, Jerry Bautista, Wojciech Maly, Jan M. Rabaey:
More Moore: foolish, feasible, or fundamentally different? 9
Floorplanning
- Qiang Ma, Evangeline F. Y. Young:
Network flow-based power optimization under timing constraints in MSV-driven floorplanning. 1-8 - Jia Wang, Hai Zhou:
Linear constraint graph for floorplan optimization with soft blocks. 9-15 - Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng:
A novel fixed-outline floorplanner with zero deadspace for hierarchical design. 16-23
Logic and high-level synthesis
- Michal Karczmarek, Arvind:
Synthesis from multi-cycle atomic actions as a solution to the timing closure problem. 24-31 - Hsuan-Po Lin, Jie-Hong Roland Jiang, Ruei-Rung Lee:
To SAT or not to SAT: Ashenhurst decomposition in a large scale. 32-37 - Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee:
Boolean factoring and decomposition of logic networks. 38-44 - Tsutomu Sasao:
On the numbers of variables to represent sparse logic functions. 45-51
Test power and temperature control
- Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara:
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. 52-58 - David R. Bild, Sanchit Misra, Thidapat Chantem, Prabhat Kumar, Robert P. Dick, Xiaobo Sharon Hu
Temperature-aware test scheduling for multiprocessor systems-on-chip. 59-66 - Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu
On capture power-aware test data compression for scan-based testing. 67-72
Simulation and optimization of analog systems
- Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif:
MAPS: multi-algorithm parallel circuit simulation. 73-78 - Guo Yu, Peng Li:
Yield-aware hierarchical optimization of large analog integrated circuits. 79-84 - Chenjie Gu, Jaijeet S. Roychowdhury:
Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems. 85-92
Physical synthesis and optimization
- Huan Ren, Shantanu Dutt:
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure. 93-100 - Yifang Liu, Rupesh S. Shelar, Jiang Hu:
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. 101-106 - Tai-Hsuan Wu, Azadeh Davoodi:
PaRS: fast and near-optimal grid-based cell sizing for library-based design. 107-111 - Shiyan Hu, Zhuo Li, Charles J. Alpert:
A polynomial time approximation scheme for timing constrained minimum cost layer assignment. 112-115 - Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David T. Blaauw:
On the decreasing significance of large standard cells in technology mapping. 116-121
Decision procedures in verification
- Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan:
Verification of arithmetic datapaths using polynomial function models and congruence solving. 122-128 - Gianpiero Cabodi, Paolo Camurati, Marco Murciano:
Automated abstraction by incremental refinement in interpolant-based model checking. 129-136 - Brian Keng, Hratch Mangassarian, Andreas G. Veneris:
A succinct memory model for automated design debugging. 137-142 - John D. Backes, Brian Fett, Marc D. Riedel
The analysis of cyclic circuits with Boolean satisfiability. 143-148
Power estimation and optimization
- Youngjin Cho, Younghyun Kim
System-level power estimation using an on-chip bus performance monitoring unit. 149-154 - Mohammad Ghasemazar, Massoud Pedram:
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing. 155-160 - Hao Xu, Wen-Ben Jone, Ranga Vemuri
Accurate energy breakeven time estimation for run-time power gating. 161-168 - Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim:
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. 169-172
Recent progress in SSTA
- Khaled R. Heloue, Sari Onaissi, Farid N. Najm:
Efficient block-based parameterized timing analysis covering all potentially critical paths. 173-180 - Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu:
Adjustment-based modeling for statistical static timing analysis with high dimension of variability. 181-184 - Farinaz Koushanfar
Post-silicon timing characterization by compressed sensing. 185-189 - Amith Singhee, Sonia Singhal, Rob A. Rutenbar
Practical, fast Monte Carlo statistical static timing analysis: why and how. 190-195 - Javid Jaffari, Mohab Anis:
On efficient Monte Carlo-based statistical static timing analysis of digital circuits. 196-203
Placement
- Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan:
Pyramids: an efficient computational geometry-based approach for timing-driven placement. 204-211 - Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan
Guiding global placement with wire density. 212-217 - Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang
Constraint graph-based macro placement for modern mixed-size circuit designs. 218-223
Sequential synthesis
- Hyein Lee, Seungwhun Paik, Youngsoo Shin:
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. 224-229 - Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang:
A novel sequential circuit optimization with clock gating logic. 230-233 - Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang:
Scalable and scalably-verifiable sequential synthesis. 234-241
System-level thermal and power management
- Sushu Zhang, Karam S. Chatha:
System-level thermal aware design of applications with uncertain execution time. 242-249 - Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross:
Proactive temperature balancing for low cost thermal management in MPSoCs. 250-257 - Omer Khan, Sandip Kundu:
A framework for predictive dynamic temperature management of microprocessor systems. 258-263 - Wooyoung Jang, Duo Ding, David Z. Pan:
A voltage-frequency island aware energy optimization framework for networks-on-chip. 264-269
Modeling and simulation of process variability
- Hamed F. Dadgour, Vivek De, Kaustav Banerjee:
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. 270-277 - Yiming Li, Chih-Hong Hwang, Ta-Ching Yeh, Tien-Yeh Li:
Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits. 278-285 - Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu
A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. 286-291 - Victoria Wang, Dejan Markovic:
Linear analysis of random process variability. 292-296
Placement and beyond
- Tao Xu, Krishnendu Chakrabarty
Design and optimization of a digital microfluidic biochip for protein crystallization. 297-301 - Hushrav Mogal, Kia Bazargan:
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. 302-305 - Martin Strasser, Michael Eick, Helmut Gräb, Ulf Schlichtmann
Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. 306-313
Circuit and system optimization and modeling
- Ranko Sredojevic, Vladimir Stojanovic:
Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example. 314-321 - Lara Dolecek, Masood Qazi, Devavrat Shah, Anantha P. Chandrakasan:
Breaking the simulation barrier: SRAM evaluation through norm minimization. 322-329 - Aida Todri
Power supply noise aware workload assignment for multi-core systems. 330-337
Global routing
- Yen-Jung Chang, Yu-Ting Lee, Ting-Chi Wang:
NTHU-Route 2.0: a fast and stable global router. 338-343 - Yanheng Zhang, Yue Xu, Chris Chu:
FastRoute3.0: a fast and high quality global router based on virtual capacity. 344-349 - Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang
Multi-layer global routing considering via and wire capacities. 350-355
System-level simulation
- Nicolas Blanc, Daniel Kroening
Race analysis for SystemC using model checking. 356-363 - Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman:
MC-Sim: an efficient simulation tool for MPSoC designs. 364-371 - Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang:
Verifying external interrupts of embedded microprocessor in SoC with on-chip bus. 372-377
Analog and memory design enablers
- Wei Dong, Peng Li, Garng M. Huang:
SRAM dynamic stability: theory, variability and analysis. 378-385 - Jaeha Kim, Brian S. Leibowitz, Metha Jeeradit:
Impulse sensitivity function analysis of periodic circuits. 386-391 - Trent McConaghy, Pieter Palmers, Georges G. E. Gielen
Automated extraction of expert knowledge in analog topology selection and sizing. 392-395 - Peng Gao
Importance sampled circuit learning ensembles for robust analog IC design. 396-399
Embedded tutorial: Graphene electronics: design and CAD challenges and opportunities
- Azad Naeemi
Physical models for electron transport in graphene nanoribbons and their junctions. 400-405 - Kenneth L. Shepard, Inanc Meric, Philip Kim:
Characterization and modeling of graphene field-effect devices. 406-411 - Kartik Mohanram, Jing Guo:
Graphene nanoribbon FETs: technology exploration and CAD. 412-415
Physical design for performance improvement & noise immunity
- Yesin Ryu, Taewhan Kim:
Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. 416-419 - Takashi Enami, Masanori Hashimoto
Decoupling capacitance allocation for timing with statistical noise model and timing analysis. 420-425 - Po-Yuan Chen, Che-Yu Liu, TingTing Hwang:
Transition-aware decoupling-capacitor allocation in power noise reduction. 426-429 - Fan Mo, Robert K. Brayton:
Placement based multiplier rewiring for cell-based designs. 430-433
Novel design methodologies for system architecture
- Timothy Kam, Michael Kishinevsky, Jordi Cortadella
Correct-by-construction microarchitectural pipelining. 434-441 - Dmitry Bufistov, Jorge Júlvez, Jordi Cortadella
Performance optimization of elastic systems using buffer resizing and buffer insertion. 442-448 - Gennette Gill, Vishal Gupta, Montek Singh:
Performance estimation and slack matching for pipelined asynchronous architectures with choice. 449-456 - Myong Hyon Cho, Chih-Chi Cheng, Michel A. Kinsy, G. Edward Suh, Srinivas Devadas:
Diastolic arrays: throughput-driven reconfigurable computing. 457-464
DFM methods for advanced lithography
- Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao:
Layout decomposition for double patterning lithography. 465-472 - Shayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky:
Electrically driven optical proximity correction based on linear programming. 473-479 - Jinyu Zhang, Wei Xiong, Yan Wang, Zhiping Yu, Min-Chun Tsai:
A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique. 480-487 - Jae-Seok Yang, David Z. Pan:
Overlay aware interconnect and timing variation modeling for double patterning technology. 488-493 - Alexey Lvov, Ulrich Finkler:
Exact basic geometric operations on arbitrary angle polygons using only fixed size integer coordinates. 494-498
Advances in routing
- Tan Yan, Martin D. F. Wong
BSG-Route: a length-matching router for general topology. 499-505 - Minsik Cho, Yongchan Ban, David Z. Pan:
Double patterning technology friendly detailed routing. 506-511 - Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang
Routing for chip-package-board co-design considering differential pairs. 512-517 - Jia-Wei Fang, Yao-Wen Chang
Area-I/O flip-chip routing for chip-package co-design. 518-522 - Liang Li, Evangeline F. Y. Young:
Obstacle-avoiding rectilinear Steiner tree construction. 523-528
System-level optimization issues in highly parallel architectures
- Kevin Brownell, Gu-Yeon Wei, David M. Brooks:
Evaluation of voltage interpolation to address process variations. 529-536 - Ravishankar Rao, Sarma B. K. Vrudhula:
Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. 537-542 - Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel:
ROAdNoC: runtime observability for an adaptive network on chip architecture. 543-548 - Talal Bonny
FBT: filled buffer technique to reduce code size for VLIW processors. 549-554 - Yi Zhu, Michael B. Taylor, Scott B. Baden, Chung-Kuan Cheng:
Advancing supercomputer performance through interconnection topology synthesis. 555-558
Advances in embedded systems
- B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran:
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. 559-564 - Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Ozcan Ozturk:
SPM management using Markov chain based data access prediction. 565-569 - Love Singhal, Elaheh Bozorgzadeh:
Process variation aware system-level task allocation using stochastic ordering of delay distributions. 570-574 - Sanjit A. Seshia, Alexander Rakhlin:
Game-theoretic timing analysis. 575-582 - Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin:
Integrated code and data placement in two-dimensional mesh based chip multiprocessors. 583-588
Alternative circuit fabrics
- Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. 589-592 - Tamer Ragheb, Yehia Massoud:
On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications. 593-597 - Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. 598-602
Thermal analysis and optimization
- Nicholas Allec, Zyad Hassan, Li Shang, Robert P. Dick, Ronggui Yang:
ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits. 603-610 - Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala:
Parameterized transient thermal behavioral modeling for chip multiprocessors. 611-617 - Ramkumar Jayaseelan, Tulika Mitra
Temperature aware task sequencing and voltage scaling. 618-623
Path delay anomaly identification for quality and security
- Vladimir Zolotov, Jinjun Xiong
Statistical path selection for at-speed test. 624-631 - Reza M. Rad, Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic:
Power supply signal calibration techniques for improving detection resolution to hardware Trojans. 632-639 - Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta:
Path-RO: a novel on-chip critical path delay measurement under process variations. 640-646
Techniques for next generation interconnect modeling
- Zhuo Feng, Peng Li:
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms. 647-654 - Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh:
Efficient and accurate eye diagram prediction for high speed signaling. 655-661 - Tarek A. El-Moselhy, Ibrahim M. Elfadel
A capacitance solver for incremental variation-aware extraction. 662-669
Security issues in ICs
- Mehrdad Majzoobi, Farinaz Koushanfar
Lightweight secure PUFs. 670-673 - Rajat Subhra Chakraborty, Swarup Bhunia
Hardware protection and authentication through netlist level obfuscation. 674-677 - Jude Angelo Ambrose, Sri Parameswaran
MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. 678-684
Modeling approaches for reliability and stress analysis
- Natasa Miskov-Zivanov, Kai-Chiang Wu, Diana Marculescu
Process variability-aware transient fault modeling and analysis. 685-690 - Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw:
STEEL: a technique for stress-enhanced standard cell library design. 691-697 - Kaviraj Chopra, Cheng Zhuo, David T. Blaauw, Dennis Sylvester:
A statistical approach for full-chip gate-oxide reliability analysis. 698-705
Improving FPGA reliability
- Yu Hu, Zhe Feng, Lei He, Rupak Majumdar:
Robust FPGA resynthesis based on fault-tolerant Boolean matching. 706-713 - Amit Agarwal, Jason Cong, Brian Tagiku:
Fault tolerant placement and defect reconfiguration for nano-FPGAs. 714-721 - Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan:
Thermal-aware reliability analysis for platform FPGAs. 722-727
Advances in model order reduction
- Bradley N. Bond, Luca Daniel:
Guaranteed stable projection-based model reduction for indefinite and unstable linear systems. 728-735 - Zuochang Ye, Dmitry Vasilyev, Zhenhai Zhu, Joel R. Phillips:
Sparse implicit projection (SIP) for reduction of general many-terminal networks. 736-743 - Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Lifeng Wu:
Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method. 744-749
Design techniques for emerging technologies
- Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King Liu, Vladimir Stojanovic, Elad Alon:
Integrated circuit design with NEM relays. 750-757 - Brian Fett, Marc D. Riedel
Module locking in biochemical synthesis. 758-764 - Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud:
Robust reconfigurable filter design using analytic variability quantification techniques. 765-770
Embedded tutorial: Learning from silicon: correlating measurements, models and design
- Anne Gattiker:
Using test data to improve IC quality and yield. 771-777 - Chandramouli V. Kashyap, Pouria Bastani, Kip Killpack, Chirayu S. Amin:
Silicon feedback to improve frequency of high-performance microprocessors: an overview. 778-782
Exploiting logic constraints for noise analysis
- Ruiming Li, An-Jui Shey, Michel Laudes:
Incorporating logic exclusivity (LE) constraints in noise analysis using gain guided backtracking method. 783-789 - Debjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam:
Constrained aggressor set selection for maximum coupling noise. 790-796 - Weiqing Guo, Yu Zhong, Tom Burd:
Context-sensitive static transistor-level IR analysis. 797-802
Advances in oscillator macromodeling
- Xiaolue Lai:
Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysis. 803-806 - Mark M. Gourary, Sergey G. Rusakov
Smoothed form of nonlinear phase macromodel for oscillators. 807-814 - Prateek Bhansali, Shweta Srivastava, Xiaolue Lai, Jaijeet S. Roychowdhury:
Comprehensive procedure for fast and accurate coupled oscillator network simulation. 815-820
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