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Zhuo Li 0001
Person information
- affiliation: Cadence Design Systems Inc, San Jose, CA, USA
- affiliation: IBM Austin Research Lab, Austin, TX, USA
- affiliation (PhD 2005): Texas A&M University, College Station, TX, USA
Other persons with the same name
- Zhuo Li — disambiguation page
- Zhuo Li 0002 — University of Texas at Arlington
- Zhuo Li 0003
— Beijing Information Science and Technology University, Beijing Key Laboratory of Internet Culture and Digital Dissemination Research, China (and 1 more)
- Zhuo Li 0004 — University of Delaware, Human Language Technology Laboratory
- Zhuo Li 0005 — Beihang University, School of Electronics and Information Engineering, Beijing, China
- Zhuo Li 0006 — Xiangtan University, Dept. of Mathematics
- Zhuo Li 0007
- Zhuo Li 0008 — Utah State University
- Zhuo Li 0009
- Zhuo Li 0010
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2020 – today
- 2020
- [j19]Zhuo Li
Conference Report From The 57th Design Automation Conference. IEEE Des. Test 37(6): 99-101 (2020)
2010 – 2019
- 2018
- [j18]Yibo Lin
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1237-1250 (2018) - [c58]Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh:
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD 2018: 10-17 - 2017
- [j17]Yibo Lin
Stitch aware detailed placement for multiple E-beam lithography. Integr. 58: 47-54 (2017) - 2016
- [c57]Yibo Lin
Stitch aware detailed placement for multiple e-beam lithography. ASP-DAC 2016: 186-191 - [c56]Yibo Lin
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD 2016: 7 - 2015
- [j16]Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 726-739 (2015) - 2014
- [j15]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. 19(2): 17:1-17:37 (2014) - [c55]Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze:
Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP 2014: 3:1-3:5 - 2013
- [j14]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 228-241 (2013) - [c54]Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan:
Routing congestion estimation with real design constraints. DAC 2013: 92:1-92:8 - [c53]Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar:
CATALYST: planning layer directives for effective design closure. DATE 2013: 1873-1878 - [c52]Iris Hui-Ru Jiang, Zhuo Li, Hwei-Tseng Wang, Natarajan Viswanathan:
The overview of 2013 CAD contest at ICCAD. ICCAD 2013: 264 - [c51]Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert:
ICCAD-2013 CAD contest in placement finishing and benchmark suite. ICCAD 2013: 268-270 - [c50]Shayak Banerjee, Zhuo Li, Sani R. Nassif:
ICCAD-2013 CAD contest in mask optimization and benchmark suite. ICCAD 2013: 271-274 - [c49]Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan:
Clock power minimization using structured latch templates and decision tree induction. ICCAD 2013: 599-606 - 2012
- [j13]Zhuo Li, Nancy Ying Zhou, Weiping Shi:
$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 437-441 (2012) - [c48]Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou:
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC 2012: 465-470 - [c47]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
GLARE: global and local wiring aware routability evaluation. DAC 2012: 768-773 - [c46]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
The DAC 2012 routability-driven placement contest and benchmark suite. DAC 2012: 774-782 - [c45]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif:
Yield estimation via multi-cones. DAC 2012: 1107-1112 - [c44]Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward:
Placement: Hot or Not? ICCAD 2012: 283-290 - [c43]Iris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li:
Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. ICCAD 2012: 341 - [c42]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. ICCAD 2012: 345-348 - [c41]Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif:
2012 TAU power grid simulation contest: Benchmark suite and results. ICCAD 2012: 643-646 - [c40]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Keep it straight: teaching placement how to better handle designs with datapaths. ISPD 2012: 79-86 - 2011
- [j12]David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov:
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro 31(4): 51-62 (2011) - [j11]Shiyan Hu, Zhuo Li, Yangdong Deng:
CAD for Gigascale SoC Design and Verification Solutions. VLSI Design 2011: 398390:1-398390:2 (2011) - [j10]Nancy Ying Zhou
Shedding Physical Synthesis Area Bloat. VLSI Design 2011: 503025:1-503025:10 (2011) - [c39]Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif:
2011 TAU power grid simulation contest: Benchmark suite and results. ICCAD 2011: 478-481 - [c38]Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.:
Quantifying academic placer performance on custom designs. ISPD 2011: 91-98 - [c37]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy:
The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD 2011: 141-146 - 2010
- [c36]Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn:
Detecting tangled logic structures in VLSI netlists. DAC 2010: 603-608 - [c35]Taraneh Taghavi, Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Andrew D. Huber, Shyam Ramji:
New placement prediction and mitigation techniques for local routing congestion. ICCAD 2010: 621-624 - [c34]Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez:
What makes a design difficult to route. ISPD 2010: 7-12 - [c33]Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou:
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD 2010: 75-82 - [c32]Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu:
ITOP: integrating timing optimization within placement. ISPD 2010: 83-90
2000 – 2009
- 2009
- [j9]Shiyan Hu
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 580-584 (2009) - [c31]Shiyan Hu, Zhuo Li, Charles J. Alpert:
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. DAC 2009: 424-429 - [c30]Shiyan Hu, Zhuo Li, Charles J. Alpert:
A faster approximation scheme for timing driven minimum cost layer assignment. ISPD 2009: 167-174 - [c29]Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi:
The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED 2009: 607-612 - 2008
- [j8]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2156-2168 (2008) - [c28]Michael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert:
Path smoothing via discrete optimization. DAC 2008: 724-727 - [c27]Shiyan Hu, Zhuo Li, Charles J. Alpert:
A polynomial time approximation scheme for timing constrained minimum cost layer assignment. ICCAD 2008: 112-115 - [c26]Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan:
Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD 2008: 204-211 - [c25]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif:
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED 2008: 87-92 - [c24]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD 2008: 2-9 - [c23]Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia:
Fast interconnect synthesis with layer assignment. ISPD 2008: 71-77 - [c22]Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif:
A Root-Finding Method for Assessing SRAM Stability. ISQED 2008: 804-809 - [r1]Jiang Hu, Zhuo Li, Shiyan Hu:
Buffer Insertion Basics. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j7]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
Techniques for Fast Physical Synthesis. Proc. IEEE 95(3): 573-599 (2007) - [j6]Zhuo Li, Nancy Ying Zhou, Weiping Shi:
Wire Sizing for Non-Tree Topology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 872-880 (2007) - [j5]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2009-2022 (2007) - [c21]Nancy Ying Zhou, Zhuo Li, Yuxin Tian, Weiping Shi, Frank Liu:
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. ASP-DAC 2007: 450-455 - [c20]Nancy Ying Zhou, Zhuo Li, Weiping Shi:
Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method. DAC 2007: 835-840 - [c19]Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar
Probabilistic Congestion Prediction with Partial Blockages. ISQED 2007: 841-846 - [c18]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
The nuts and bolts of physical synthesis. SLIP 2007: 89-94 - [i1]Zhuo Li, Weiping Shi:
An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types. CoRR abs/0710.4691 (2007) - 2006
- [j4]Zhuo Li, Weiping Shi:
An O(bn2) time algorithm for optimal buffer insertion with b buffer types. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 484-489 (2006) - [c17]Zhuo Li, Weiping Shi:
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks. ASP-DAC 2006: 320-325 - [c16]Mandar Waghmode, Zhuo Li, Weiping Shi:
Buffer insertion in large circuits with constructive solution search techniques. DAC 2006: 296-301 - [c15]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313 - [c14]Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi:
A new RLC buffer insertion algorithm. ICCAD 2006: 553-557 - 2005
- [b1]Zhuo Li:
Fast interconnect optimization. Texas A&M University, College Station, USA, 2005 - [j3]Weiping Shi, Zhuo Li:
A fast algorithm for optimal buffer insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 879-891 (2005) - [j2]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
Longest-path selection for delay test under process variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1924-1929 (2005) - [c13]Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18 - [c12]Zhuo Li, Weiping Shi:
An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types. DATE 2005: 1324-1329 - [c11]Sani R. Nassif, Zhuo Li:
A More Effective CEFF. ISQED 2005: 648-653 - 2004
- [c10]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
Longest path selection for delay test under process variation. ASP-DAC 2004: 98-103 - [c9]Weiping Shi, Zhuo Li, Charles J. Alpert:
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. ASP-DAC 2004: 609-614 - [c8]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
PARADE: PARAmetric Delay Evaluation under Process Variation. ISQED 2004: 276-280 - [c7]Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran:
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. ITC 2004: 223-231 - [c6]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. MTV 2004: 97-102 - [c5]Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi:
A Statistical Fault Coverage Metric for Realistic Path Delay Faults. VTS 2004: 37-42 - 2003
- [j1]Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A circuit level fault model for resistive bridges. ACM Trans. Design Autom. Electr. Syst. 8(4): 546-559 (2003) - [c4]Weiping Shi, Zhuo Li:
An O(nlogn) time algorithm for optimal buffer insertion. DAC 2003: 580-585 - [c3]Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi:
CodSim -- A Combined Delay Fault Simulator. DFT 2003: 79- - [c2]Zhuo Li, Xiang Lu, Weiping Shi:
Process variation dimension reduction based on SVD. ISCAS (4) 2003: 672-675 - [c1]Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A Circuit Level Fault Model for Resistive Opens and Bridges. VTS 2003: 379-384
Coauthor Index
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