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Michael Orshansky
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2020 – today
- 2024
- [j20]Vishnuvardhan V. Iyer
, Aditya Thimmaiah
A Hierarchical Classification Method for High-accuracy Instruction Disassembly with Near-field EM Measurements. ACM Trans. Embed. Comput. Syst. 23(1): 10:1-10:21 (2024) - [c67]Alexander Cathis
SoK Paper: Power Side-Channel Malware Detection. HASP@MICRO 2024: 1-9 - 2023
- [j19]Xiaodan Xi
A Provably Secure Strong PUF Based on LWE: Construction and Implementation. IEEE Trans. Computers 72(2): 346-359 (2023) - [c66]Zihao Deng, Benjamin Ghaemmaghami, Ashish Kumar Singh, Benjamin Y. Cho, Leo Orshansky, Mattan Erez, Michael Orshansky:
Enhancing Cross-Category Learning in Recommendation Systems with Multi-Layer Embedding Training. ACML 2023: 263-278 - [i10]Xiaodan Xi, Ge Li, Ye Wang, Yeonsoo Jeon, Michael Orshansky:
A Provably Secure Strong PUF based on LWE: Construction and Implementation. CoRR abs/2303.02802 (2023) - [i9]Zihao Deng, Xin Wang, Sayeh Sharify, Michael Orshansky:
Mixed-Precision Quantization with Cross-Layer Dependencies. CoRR abs/2307.05657 (2023) - [i8]Zihao Deng, Benjamin Ghaemmaghami, Ashish Kumar Singh, Benjamin Y. Cho, Leo Orshansky, Mattan Erez, Michael Orshansky:
Enhancing Cross-Category Learning in Recommendation Systems with Multi-Layer Embedding Training. CoRR abs/2309.15881 (2023) - [i7]Yeonsoo Jeon, Mattan Erez, Michael Orshansky:
Artemis: HE-Aware Training for Efficient Privacy-Preserving Machine Learning. CoRR abs/2310.01664 (2023) - 2022
- [j18]Ge Li
Power-based Attacks on Spatial DNN Accelerators. ACM J. Emerg. Technol. Comput. Syst. 18(3): 58:1-58:18 (2022) - [c65]Zihao Deng, Michael Orshansky:
Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM. DATE 2022: 712-717 - [c64]Aditya Thimmaiah, Vishnuvardhan V. Iyer, Andreas Gerstlauer, Michael Orshansky:
High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks. SAMOS 2022: 155-170 - 2021
- [j17]Furkan Aydin
Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols. ACM Trans. Embed. Comput. Syst. 20(6): 110:1-110:22 (2021) - [c63]Meizhi Wang
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks. CICC 2021: 1-2 - [c62]Meizhi Wang
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management. CICC 2021: 1-2 - [i6]Ge Li, Mohit Tiwari, Michael Orshansky:
Power-Based Attacks on Spatial DNN Accelerators. CoRR abs/2108.12579 (2021) - [i5]Zihao Deng, Michael Orshansky:
Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM. CoRR abs/2111.06457 (2021) - 2020
- [j16]Haoyu Zhuang
A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 135-144 (2020) - [c61]Ye Wang, Xiaodan Xi
Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks. HOST 2020: 273-283 - [i4]Benjamin Ghaemmaghami, Zihao Deng, Benjamin Y. Cho, Leo Orshansky, Ashish Kumar Singh, Mattan Erez, Michael Orshansky:
Training with Multi-Layer Embeddings for Model Reduction. CoRR abs/2006.05623 (2020)
2010 – 2019
- 2019
- [c60]Shijia Wei
Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems. HOST 2019: 111-120 - [c59]Ge Li, Vishnuvardhan V. Iyer, Michael Orshansky:
Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow. HOST 2019: 191-197 - [i3]Ye Wang, Xiaodan Xi, Michael Orshansky:
Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks. CoRR abs/1909.13441 (2019) - 2018
- [c58]Aydin Aysu, Michael Orshansky, Mohit Tiwari
Binary Ring-LWE hardware with power side-channel countermeasures. DATE 2018: 1253-1258 - [c57]Ye Wang, Michael Orshansky:
Efficient helper data reduction in SRAM PUFs via lossy compression. DATE 2018: 1453-1458 - [c56]Aydin Aysu, Youssef Tobah, Mohit Tiwari
Horizontal side-channel vulnerabilities of post-quantum key exchange protocols. HOST 2018: 81-88 - [c55]Xiaodan Xi
Fresh re-keying with strong PUFs: A new approach to side-channel security. HOST 2018: 118-125 - 2017
- [c54]Aydin Aysu, Ye Wang, Patrick Schaumont
A new maskless debiasing method for lightweight physical unclonable functions. HOST 2017: 134-139 - [c53]Amit Kumar, Cody Scarborough, Ali E. Yilmaz, Michael Orshansky:
Efficient simulation of EM side-channel attack resilience. ICCAD 2017: 123-130 - 2016
- [j15]Jaeyoung Park, Tianhao Zheng, Mattan Erez
Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1351-1360 (2016) - [c52]Meng Li, Ye Wang, Michael Orshansky:
A Monte Carlo simulation flow for SEU analysis of sequential circuits. DAC 2016: 44:1-44:6 - [c51]Ye Wang, Constantine Caramanis, Michael Orshansky:
PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation. DATE 2016: 1423-1428 - [c50]Jaeyoung Park, Michael Orshansky:
Multiple Attempt Write Strategy for Low Energy STT-RAM. ACM Great Lakes Symposium on VLSI 2016: 163-168 - [c49]Ye Wang, Constantine Caramanis
Exploiting randomness in sketching for efficient hardware implementation of machine learning applications. ICCAD 2016: 114 - 2015
- [c48]Ye Wang, Meng Li, Xinyang Yi, Zhao Song, Michael Orshansky, Constantine Caramanis
Novel power grid reduction method based on L1 regularization. DAC 2015: 93:1-93:6 - 2014
- [j14]Ashish Kumar Singh, Ku He, Constantine Caramanis
Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1159-1167 (2014) - [c47]Ye Wang, Michael Orshansky, Constantine Caramanis
Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization. DAC 2014: 164:1-164:6 - [c46]Jin Miao, Andreas Gerstlauer, Michael Orshansky:
Multi-level approximate logic synthesis under general error constraints. ICCAD 2014: 504-510 - 2013
- [j13]Mona Yousofshahi, Michael Orshansky, Kyongbum Lee
Probabilistic strain optimization under constraint uncertainty. BMC Syst. Biol. 7: 29 (2013) - [j12]Ku He, Andreas Gerstlauer, Michael Orshansky:
Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems. IEEE Trans. Circuits Syst. Video Technol. 23(6): 961-974 (2013) - [c45]Mona Yousofshahi, Michael Orshansky, Kyongbum Lee, Soha Hassoun:
Gene modification identification under flux capacity uncertainty. DAC 2013: 45:1-45:5 - [c44]Jie Han, Michael Orshansky:
Approximate computing: An emerging paradigm for energy-efficient design. ETS 2013: 1-6 - [c43]Mukund Kalyanaraman, Michael Orshansky:
Novel strong PUF based on nonlinearity of MOSFET subthreshold operation. HOST 2013: 13-18 - [c42]Jin Miao, Andreas Gerstlauer, Michael Orshansky:
Approximate logic synthesis under general error magnitude and frequency constraints. ICCAD 2013: 779-786 - [c41]Tianhao Zheng, Jaeyoung Park, Michael Orshansky, Mattan Erez
Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring. ISLPED 2013: 229-234 - [c40]Ku He, Andreas Gerstlauer, Michael Orshansky:
Low-energy digital filter design based on controlled timing error acceptance. ISQED 2013: 151-157 - 2012
- [j11]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan:
An accurate sparse-matrix based framework for statistical static timing analysis. Integr. 45(4): 365-375 (2012) - [j10]Ashish Kumar Singh, Kareem Ragab, Mario Lok, Constantine Caramanis
Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1485-1498 (2012) - [c39]Jin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky:
Modeling and synthesis of quality-energy optimal approximate adders. ICCAD 2012: 728-735 - [c38]Ku He, Andreas Gerstlauer, Michael Orshansky:
Low-energy signal processing using circuit-level timing-error acceptance. ICICDT 2012: 1-4 - [c37]Kareem Ragab, Ranjit Gharpurey, Michael Orshansky:
Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation. ISQED 2012: 143-150 - [i2]Mukund Kalyanaraman, Michael Orshansky:
Highly Secure Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation. IACR Cryptol. ePrint Arch. 2012: 413 (2012) - 2011
- [c36]Ku He, Andreas Gerstlauer, Michael Orshansky:
Controlled timing-error acceptance for low energy IDCT design. DATE 2011: 758-763 - [c35]Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky:
Coupling timing objectives with optical proximity correction for improved timing yield. ISQED 2011: 97-102 - 2010
- [c34]Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky:
Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects. CICC 2010: 1-4 - [c33]Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky:
A methodology for propagating design tolerances to shape tolerances for use in manufacturing. DATE 2010: 1273-1278 - [c32]Ashish Kumar Singh, Mario Lok, Kareem Ragab, Constantine Caramanis
An algorithm for exploiting modeling error statistics to enable robust analog optimization. ICCAD 2010: 62-69 - [c31]Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky:
SMATO: Simultaneous mask and target optimization for improving lithographic process window. ICCAD 2010: 100-106 - [c30]Mehmet Basoglu, Michael Orshansky, Mattan Erez:
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime. ISLPED 2010: 253-258
2000 – 2009
- 2009
- [j9]Michael Orshansky, Wei-Shen Wang:
Statistical analysis of circuit timing using majorization. Commun. ACM 52(8): 95-100 (2009) - [c29]Ashish Kumar Singh, Ku He, Constantine Caramanis
Mitigation of intra-array SRAM variability using adaptive voltage architecture. ICCAD 2009: 637-644 - 2008
- [b1]Michael Orshansky, Sani R. Nassif, Duane S. Boning:
Design for Manufacturability and Statistical Design - A Constructive Approach. Series on integrated circuits and systems, Springer 2008, ISBN 978-0-387-30928-6, pp. I-XIV, 1-310 - [j8]Naresh R. Shanbhag, Subhasish Mitra
The Search for Alternative Computational Paradigms. IEEE Des. Test Comput. 25(4): 334-343 (2008) - [c28]Shayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky:
Electrically driven optical proximity correction based on linear programming. ICCAD 2008: 473-479 - [c27]Bin Zhang, Michael Orshansky:
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. ISQED 2008: 774-779 - 2007
- [j7]Wei-Shen Wang, Michael Orshansky:
Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. J. Low Power Electron. 3(1): 1-12 (2007) - [j6]Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky:
Architecting a reliable CMP switch architecture. ACM Trans. Archit. Code Optim. 4(1): 2 (2007) - [j5]Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan:
A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1790-1802 (2007) - [c26]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan:
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153 - [c25]Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham:
Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI 2007: 61-66 - [c24]Ashish Kumar Singh, Hady Ali Zeineddine, Adnan Aziz, Sriram Vishwanath, Michael Orshansky:
A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions. NANOARCH 2007: 15-20 - [i1]Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky:
Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies. CoRR abs/cs/0703102 (2007) - 2006
- [j4]Wei-Shen Wang, Michael Liu, Michael Orshansky:
Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. J. Low Power Electron. 2(1): 1-7 (2006) - [j3]Wei-Shen Wang, Michael Orshansky:
Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2976-2988 (2006) - [c23]Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky:
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. DAC 2006: 161-166 - [c22]Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky:
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. DAC 2006: 522-527 - [c21]Joonsoo Kim, Michael Orshansky:
Towards formal probabilistic power-performance design space exploration. ACM Great Lakes Symposium on VLSI 2006: 229-234 - [c20]Murari Mani, Mahesh Sharma, Michael Orshansky:
Application of fast SOCP based statistical sizing in the microprocessor design flow. ACM Great Lakes Symposium on VLSI 2006: 372-375 - [c19]Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky:
BulletProof: a defect-tolerant CMP switch architecture. HPCA 2006: 5-16 - [c18]Murari Mani, Ashish Kumar Singh, Michael Orshansky:
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. ICCAD 2006: 19-26 - [c17]Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan:
An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236 - [c16]Bin Zhang, Ari Arapostathis
Analytical modeling of SRAM dynamic stability. ICCAD 2006: 315-322 - [c15]Wei-Shen Wang, Michael Orshansky:
Robust estimation of parametric yield under limited descriptions of uncertainty. ICCAD 2006: 884-890 - [c14]Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar:
Tutorial II: Variability and Its Impact on Design. ISQED 2006: 5 - [c13]Bin Zhang, Wei-Shen Wang, Michael Orshansky:
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. ISQED 2006: 755-760 - [c12]Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang:
Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips. SAC 2006: 1645-1649 - 2005
- [c11]Murari Mani, Anirudh Devgan, Michael Orshansky:
An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC 2005: 309-314 - [c10]Ashish Kumar Singh, Murari Mani, Michael Orshansky:
Statistical technology mapping for parametric yield. ICCAD 2005: 511-518 - 2004
- [c9]Michael Orshansky, Arnab Bandyopadhyay:
Fast statistical timing analysis handling arbitrary delay correlations. DAC 2004: 337-342 - [c8]Murari Mani, Michael Orshansky:
A New Statistical Optimization Algorithm for Gate Sizing. ICCD 2004: 272-277 - [c7]Michael Liu, Wei-Shen Wang, Michael Orshansky:
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. ISLPED 2004: 2-7 - 2003
- [c6]David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ISLPED 2003: 158-163 - 2002
- [j2]Michael Orshansky, Linda Milor
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 544-553 (2002) - [c5]Michael Orshansky, Kurt Keutzer:
A general probabilistic framework for worst case timing analysis. DAC 2002: 556-561 - [c4]Kurt Keutzer, Michael Orshansky:
From blind certainty to informed uncertainty. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 37-41 - 2001
- [j1]Michael Orshansky, Judy An, Chun Jiang, Bill Liu, Concetta Riccobene, Chenming Hu:
Efficient generation of pre-silicon MOS model parameters for early circuit design. IEEE J. Solid State Circuits 36(1): 156-159 (2001) - 2000
- [c3]Yu Cao, Takashi Sato
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. CICC 2000: 201-204 - [c2]Michael Orshansky, Linda Milor
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD 2000: 62-67
1990 – 1999
- 1998
- [c1]Michael Orshansky, James C. Chen, Chenming Hu:
A Statistical Performance Simulation Methodology for VLSI Circuits. DAC 1998: 402-407
Coauthor Index
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