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ACM Great Lakes Symposium on VLSI 2019: Tysons Corner, VA, USA
- Houman Homayoun, Baris Taskin, Tinoosh Mohsenin, Weisheng Zhao:
Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019. ACM 2019, ISBN 978-1-4503-6252-8
Keynote & Invited Talks
- Marilyn Wolf:
Thoughts on Edge Intelligence. 1 - Serge Leef:
Automatic Implementation of Secure Silicon. 3 - Onur Mutlu:
Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation. 5-6 - Swarup Bhunia:
Innovations in IoT for a Safe, Secure, and Sustainable Future. 7
Tech Session 1: Design and Integration of Hardware Security Primitives
- Md Tanvir Arafin
, Hao-Ting Shen, Mark M. Tehranipoor, Gang Qu:
LPN-based Device Authentication Using Resistive Memory. 9-14 - M. Ali Vosoughi, Selçuk Köse:
Leveraging On-Chip Voltage Regulators Against Fault Injection Attacks. 15-20 - Mesbah Uddin, Md Sakib Hasan
On the Theoretical Analysis of Memristor based True Random Number Generator. 21-26 - Dominik Sisejkovic
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. 27-32 - Julian Harttung, Elke Franz, Sadia Moriam, Paul Walther:
Lightweight Authenticated Encryption for Network-on-Chip Communications. 33-38
Tech Session 2: VLSI Circuits and Power Aware Design
- Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method. 39-44 - Shaahin Angizi, Deliang Fan:
GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing. 45-50 - Tati Erlina, Yan Chen, Renyuan Zhang, Yasuhiko Nakashima:
An Efficient Time-based Stochastic Computing Circuitry Employing Neuron-MOS. 51-56 - Vikas Vinayaka, Sachin P. Namboodiri, Shadden Abdalla, Bryan Kerstetter, Francisco Mata-carlos, Daniel Senda, James Skelly, Angsuman Roy, R. Jacob Baker:
Monolithic 8x8 SiPM with 4-bit Current-Mode Flash ADC with Tunable Dynamic Range. 57-62
Tech Session 3: : VLSI for Machine Learning and Artificial Intelligence
- Shasha Guo, Lei Wang, Shuquan Wang, Yu Deng, Zhijie Yang
A Systolic SNN Inference Accelerator and its Co-optimized Software Framework. 63-68 - Daniele Jahier Pagliari
Dynamic Beam Width Tuning for Energy-Efficient Recurrent Neural Networks. 69-74 - Gaoming Du, Chao Tian, Zhenmin Li, Duoli Zhang, Yongsheng Yin, Yiming Ouyang:
Efficient Softmax Hardware Architecture for Deep Neural Networks. 75-80 - Mengshu Sun, Pu Zhao
HSIM-DNN: Hardware Simulator for Computation-, Storage- and Power-Efficient Deep Neural Networks. 81-86
Tech Session 4: Next Generation Interconnect: Architecture to Physical Design
- Sunwoong Kim
An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA. 87-92 - Zhengjie Li, Yuanlong Xiao
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. 93-98 - Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman:
Low Voltage Clock Tree Synthesis with Local Gate Clusters. 99-104
Tech Session 5: Designing robust VLSI circuits. From approximate computing to hardware security
- Mahabubul Alam, Swaroop Ghosh, Sujay S. Hosur:
TOIC: Timing Obfuscated Integrated Circuits. 105-110 - Md. Badruddoja Majumder, Md Sakib Hasan
Design for Eliminating Operation Specific Power Signatures from Digital Logic. 111-116 - Ali Abbasinasab, Malgorzata Marek-Sadowska:
Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration. 117-122 - Sayandeep Sanyal, Shan Pavan Pani Krishna Garapati, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya:
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis. 123-128 - Yan Verdeja Herms, Yanjing Li:
Crash Skipping: A Minimal-Cost Framework for Efficient Error Recovery in Approximate Computing Environments. 129-134
Tech Session 6: Emerging Computing & Post-CMOS Technologies
- Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao:
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. 135-140 - Bingzhe Li
Low Cost Hybrid Spin-CMOS Compressor for Stochastic Neural Networks. 141-146 - Zongxian Yang, Yixiao Ma, Lan Wei:
Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory Computing. 147-152 - Linus Witschen, Hassan Ghasemzadeh Mohammadi, Matthias Artmann, Marco Platzner:
Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. 153-158
Tech Session 7: Physical Design and Obfuscation
- Anton Sorokin, Nikolay Ryzhenko:
SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean Routing. 159-164 - Chengmo Yang, Yuan Xue:
A Scalable and Process Variation Aware NVM-FPGA Placement Algorithm. 165-170 - Bo Hu, Jingxiang Tian, Mustafa M. Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. 171-176 - Mohammad T. Khasawneh, Patrick H. Madden:
HydraRoute: A Novel Approach to Circuit Routing. 177-182
Tech Session 8: Quantum Circuits and Emerging Technologies
- Ghasem Pasandi, Massoud Pedram:
Balanced Factorization and Rewriting Algorithms for Synthesizing Single Flux Quantum Logic Circuits. 183-188 - Ruizhe Cai, Olivia Chen
A Majority Logic Synthesis Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits. 189-194 - Chengmo Yang, Zeyu Chen:
A Processing-In-Memory Implementation of SHA-3 Using a Voltage-Gated Spin Hall-Effect Driven MTJ-based Crossbar. 195-200 - Saransh Gupta, Mohsen Imani, Tajana Rosing:
Exploring Processing In-Memory for Different Technologies. 201-206
Tech Session 9: Towards Fast, Efficient, and Robust Memory
- William Andrew Simon, Yasir Mahmood Qureshi, Alexandre Levisse, Marina Zapater, David Atienza:
BLADE: A BitLine Accelerator for Devices on the Edge. 207-212 - Sukarn Agarwal
Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction. 213-218 - Mahmoud Namazi, Hosein Mohammadi Makrani, Zhi Tian, Setareh Rafatirad, Mohamad Hosein Akbari, Avesta Sasan, Houman Homayoun:
Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image Stitching. 219-224 - Sheel Sindhu Manohar
Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks. 225-230
Tech Session 10: MSE
- Erik Brunvand:
Extending Student Labs with SMT Circuit Implementation. 231-236 - Aydin Aysu:
Teaching the Next Generation of Cryptographic Hardware Design to the Next Generation of Engineers. 237-242 - Han Wan, Kangxu Liu, Jiazhen Lin, Xiaopeng Gao:
A Web-based Remote FPGA Laboratory for Computer Organization Course. 243-248 - Jacob Covey, Mark C. Johnson:
System-on-a-Chip Design as a Platform for Teaching Design and Design Flow Integration. 249-253
Poster Sessions I, II
- Joonseop Sim, Saransh Gupta, Mohsen Imani, Yeseong Kim, Tajana Rosing:
UPIM: Unipolar Switching Logic for High Density Processing-in-Memory Applications. 255-258 - SangGi Do, Mingyu Woo
Fence-Region-Aware Mixed-Height Standard Cell Legalization. 259-262 - Milad Ghorbani Moghaddam, Cristinel Ababei:
A Case for Heterogeneous Network-on-Chip Based H.264 Video Decoders. 263-266 - Xuedi Wang, Xueqing Li, Longqiang Lai, Huazhong Yang:
A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°C. 267-270 - Yu Pan, Peng Ouyang, Yinglin Zhao, Shouyi Yin, Youguang Zhang, Shaojun Wei, Weisheng Zhao:
A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network. 271-274 - Bingzhe Li
TASecure: Temperature-Aware Secure Deletion Scheme for Solid State Drives. 275-278 - Xingye Liu, Paul Ampadu:
An Asymmetric Dual Output On-Chip DC-DC Converter for Dynamic Workloads. 279-282 - Jilan Lin
CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators. 283-286 - S. V. Sandeep Avvaru, Keshab K. Parhi
Feed-Forward XOR PUFs: Reliability and Attack-Resistance Analysis. 287-290 - Zhiqi Zhu, Farah Naz Taher, Benjamin Carrión Schäfer:
Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware Accelerators. 291-294 - Minjun Seo, Roman Lysecky:
Automatic Extraction of Requirements from State-based Hardware Designs for Runtime Verification. 295-298 - Kyle Kuan, Tosiron Adegbija:
MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache. 299-302 - Faris S. Alghareb
Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State Storage. 303-306 - Mehran Goli
Automated Analysis of Virtual Prototypes at Electronic System Level. 307-310 - Wenjie Xiong
Dynamic Physically Unclonable Functions. 311-314 - Genggeng Liu
RDTA: An Efficient Routability-Driven Track Assignment Algorithm. 315-318 - Hongyu Fang, Milos Doroslovacki, Guru Venkataramani:
EraseMe: A Defense Mechanism against Information Leakage exploiting GPU Memory. 319-322 - Peng Cao, Jiangping Wu, Zhiyuan Liu, Jingjing Guo, Jun Yang, Longxing Shi:
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region. 323-326 - Brian Worek, Paul Ampadu:
Enabling Approximate Storage through Lossy Media Data Compression. 327-330 - Jianqi Chen, Benjamin Carrión Schäfer:
Thermal Fingerprinting of FPGA Designs through High-Level Synthesis. 331-334 - Fatemeh Tehranipoor, Nima Karimian, Mehran Mozaffari Kermani
Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit Attack. 335-338 - Baogang Zhang
STAT: Mean and Variance Characterization for Robust Inference of DNNs on Memristor-based Platforms. 339-342 - Jiafeng Xie, Chiou-Yng Lee:
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field. 343-346 - Li Yang, Zhezhi He, Deliang Fan:
Binarized Depthwise Separable Neural Network for Object Tracking in FPGA. 347-350 - Chengyu Hu, Qinghua Duan, Liran Hu, Peng Lu, Zhengjie Li, Meng Yang, Jian Wang, Jinmei Lai:
An Analytical-based Hybrid Algorithm for FPGA Placement. 351-354 - Shenghou Ma, Paul Ampadu:
Approximate Memory with Approximate DCT. 355-358 - Soheil Salehi
AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Sparse Signals. 359-362 - Soheil Salehi, Ramtin Zand
Clockless Spin-based Look-Up Tables with Wide Read Margin. 363-366 - Karunveer Singh, Rishabh Gupta, Vikram Gupta, Arash Fayyazi, Massoud Pedram, Shahin Nazarian:
A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning. 367-370
Special Session 1: In-Memory Processing for Future Electronics
- Akhilesh Jaiswal, Amogh Agrawal, Indranil Chakraborty, Mustafa Fayez Ali, Kaushik Roy:
Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAM. 371 - Ann Franchesca Laguna, Xunzhao Yin, Dayane Alfenas Reis
Ferroelectric FET Based In-Memory Computing for Few-Shot Learning. 373-378 - Masoud Zabihi, Zhengyang Zhao, Zamshed I. Chowdhury, Salonik Resch, Mahendra DC, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar:
True In-memory Computing with the CRAM: From Technology to Applications. 379 - Bing Li, Bonan Yan, Hai Li:
An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications. 381-386
Special Session 2: Approximate Computing Systems Design: Energy Efficiency and Security Implications
- Pruthvy Yellu, Novak Boskov, Michel A. Kinsy, Qiaoyan Yu:
Security Threats in Approximate Computing Systems. 387-392 - Honglan Jiang, Francisco J. H. Santiago, Mohammad Saeed Ansari, Leibo Liu, Bruce F. Cockburn, Fabrizio Lombardi, Jie Han:
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints. 393-398 - Md Farhadur Reza
Approximate Communication Strategies for Energy-Efficient and High Performance NoC: Opportunities and Challenges. 399-404 - Ye Wang, Qian Xu, Gang Qu, Jian Dong:
Information Hiding behind Approximate Computation. 405-410 - Tiago A. O. Alves, Felipe M. G. França
MLPrivacyGuard: Defeating Confidence Information based Model Inversion Attacks on Machine Learning Systems. 411-415
Special Session 3: Recent Advances in Near and In-Memory Computing Circuit ?
- Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok:
XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism. 417-422 - Fan Chen, Linghao Song
Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM. 423-428 - Mohsen Imani, Saransh Gupta, Yeseong Kim, Minxuan Zhou, Tajana Rosing:
DigitalPIM: Digital-based Processing In-Memory for Big Data Acceleration. 429-434 - Yuyao Kong, Jun Yang:
In-memory Processing based on Time-domain Circuit. 435-438
Special Session 4: Opportunities and Challenges for Emerging Monolithic 3D Integrated Circuits
- Prachi Shukla, Ayse K. Coskun
An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs. 439-444 - Sai Surya Kiran Pentapati, Da Eun Shim, Sung Kyu Lim
Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary. 445-450 - Nikolaos Sketopoulos, Christos P. Sotiriou, Vasileios Samaras:
Investigation and Trade-offs in 3DIC Partitioning Methodologies: N/A. 451-455 - Abhishek Koneru, Krishnendu Chakrabarty
Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits. 457-462 - Mohamed M. Sabry Aly:
N3XT Monolithic 3D Energy-Efficient Computing Systems. 463
Special Session 5: Robust IC Authentication and Protected Intellectual Property: A Special Session on Hardware Security
- Nima Karimian, Fatemeh Tehranipoor:
How to Generate Robust Keys from Noisy DRAMs? 465-469 - Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
Threats on Logic Locking: A Decade Later. 471-476 - Gaurav Kolhe, Sai Manoj P. D., Setareh Rafatirad, Hamid Mahmoodi, Avesta Sasan, Houman Homayoun:
On Custom LUT-based Obfuscation. 477-482 - Kyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis:
Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies. 483-488
Special Session 6: Neuromorphic Computing and Deep Neural Network
- Adarsha Balaji, Salim Ullah, Anup Das
Design Methodology for Embedded Approximate Artificial Neural Networks. 489-494 - Adarsha Balaji, Yuefeng Wu, Anup Das
Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing. 495-499 - Hongjia Li, Ning Liu, Xiaolong Ma, Sheng Lin, Shaokai Ye, Tianyun Zhang, Xue Lin, Wenyao Xu, Yanzhi Wang:
ADMM-based Weight Pruning for Real-Time Deep Learning Acceleration on Mobile Devices. 501-506 - Bharat Prakash, Mark Horton, Nicholas R. Waytowich, William David Hairston, Tim Oates, Tinoosh Mohsenin:
On the use of Deep Autoencoders for Efficient Embedded Reinforcement Learning. 507-512
Panelist Position Papers
- Hoda Aghaei Khouzani, Chengmo Yang:
Tuning Track-based NVM Caches for Low-Power IoT Devices. 513-518 - Sina Shahhosseini, Iman Azimi
Dynamic Computation Migration at the Edge: Is There an Optimal Choice? 519-524 - Himanshu Thapliyal
Solving Energy and Cybersecurity Constraints in IoT Devices Using Energy Recovery Computing. 525-530 - Tosiron Adegbija, Roman Lysecky, Vinu Vijay Kumar:
Right-Provisioned IoT Edge Computing: An Overview. 531-536 - Michel A. Kinsy, Novak Boskov:
Secure Computing Systems Design Through Formal Micro-Contracts. 537-542
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