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Shuangchen Li
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2020 – today
- 2023
- [j16]Guiming Wu
, Qianwen He
E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption. IEEE Micro 43(5): 88-96 (2023) - [c53]Beilei Wang, Shuangchen Li
Structure-fused deep 3D hierarchical network: A bioluminescence tomography scheme for different imaging objects. EMBC 2023: 1-5 - [c52]Shulin Zeng
DF-GAS: a Distributed FPGA-as-a-Service Architecture towards Billion-Scale Graph-based Approximate Nearest Neighbor Search. MICRO 2023: 283-296 - [c51]Zheng Qu
TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization. MICRO 2023: 452-464 - [c50]Heng Zhang, Xiaowei He, Hongbo Guo, Yanqiu Liu, Shuangchen Li
Based on model-driven fast iterative shrinkage thresholding network for bioluminescence tomography reconstruction. Image Processing 2023 - [c49]Lizhi Zhang, Beilei Wang, Xiaowei He, Shuangchen Li
Multi-target reconstruction of fluorescence molecular tomography based on blind source separation. Image Processing 2023 - 2022
- [j15]Linyong Huang
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. IEEE Access 10: 46796-46807 (2022) - [j14]Linyong Huang, Zhe Zhang, Zhaoyang Du
EPQuant: A Graph Neural Network compression approach based on product quantization. Neurocomputing 503: 49-61 (2022) - [j13]Bangyan Wang
Efficient Processing of Sparse Tensor Decomposition via Unified Abstraction and PE-Interactive Architecture. IEEE Trans. Computers 71(2): 266-281 (2022) - [c48]Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. ISCA 2022: 946-961 - [c47]Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie:
184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. ISSCC 2022: 1-3 - 2021
- [j12]Peng Gu
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1586-1599 (2021) - [c46]Shuangchen Li
End-To-End Bioluminescence Tomography Reconstruction Based On Convolution Neural Network Scheme. EMBC 2021: 3634-3639 - [c45]Heng Zhang, Hongbo Guo, Shuangchen Li
L1-L2 Minimization Via A Proximal Operator For Fluorescence Molecular Tomography. EMBC 2021: 3640-3645 - [c44]Jilan Lin, Shuangchen Li, Yufei Ding, Yuan Xie:
Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications. ICCAD 2021: 1-9 - [c43]Yuke Wang, Boyuan Feng, Gushu Li, Shuangchen Li, Lei Deng, Yuan Xie, Yufei Ding:
GNNAdvisor: An Adaptive and Efficient Runtime System for GNN Acceleration on GPUs. OSDI 2021: 515-531 - 2020
- [j11]Lei Deng
Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation. IEEE J. Solid State Circuits 55(8): 2228-2246 (2020) - [j10]Xinfeng Xie
NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs. ACM Trans. Archit. Code Optim. 17(4): 31:1-31:25 (2020) - [c42]Xing Hu, Ling Liang, Shuangchen Li, Lei Deng
DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints. ASPLOS 2020: 385-399 - [c41]Marzieh Lenjani, Patricia Gonzalez-Guerrero, Elaheh Sadredini
Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators. HPCA 2020: 556-569 - [c40]Wenqin Huangfu, Krishna T. Malladi, Shuangchen Li, Peng Gu, Yuan Xie:
NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting. ICCAD 2020: 28:1-28:9 - [c39]Zhaodong Chen, Mingyu Yan, Maohua Zhu, Lei Deng
fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU. ICCAD 2020: 60:1-60:9 - [c38]Liu Liu, Lei Deng, Zhaodong Chen, Yuke Wang, Shuangchen Li, Jingwei Zhang, Yihua Yang, Zhenyu Gu, Yufei Ding, Yuan Xie:
Boosting Deep Neural Network Efficiency with Dual-Module Inference. ICML 2020: 6205-6215 - [c37]Liu Liu
DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture. MICRO 2020: 738-750 - [i4]Yuke Wang, Boyuan Feng, Gushu Li, Shuangchen Li, Lei Deng, Yuan Xie, Yufei Ding:
GNNAdvisor: An Efficient Runtime System for GNN Acceleration on GPUs. CoRR abs/2006.06608 (2020)
2010 – 2019
- 2019
- [j9]Xinfeng Xie
NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs. IEEE Comput. Archit. Lett. 18(1): 38-42 (2019) - [j8]Shouyi Yin
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. IEEE Trans. Parallel Distributed Syst. 30(1): 146-160 (2019) - [c36]Jinshan Yue, Yongpan Liu, Fang Su, Shuangchen Li, Zhe Yuan, Zhibo Wang, Wenyu Sun, Xueqing Li, Huazhong Yang:
AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip. ASP-DAC 2019: 146-151 - [c35]Yu Ji, Youyang Zhang, Xinfeng Xie, Shuangchen Li, Peiqi Wang, Xing Hu, Youhui Zhang, Yuan Xie:
FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture. ASPLOS 2019: 733-747 - [c34]Kun Wu
Memory-Bound Proof-of-Work Acceleration for Blockchain Applications. DAC 2019: 177 - [c33]Alvin Oliver Glova, Itir Akgun
Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory. DATE 2019: 800-805 - [c32]Yang Zhao
Memory Trojan Attack on Neural Network Accelerators. DATE 2019: 1415-1420 - [c31]Xinfeng Xie, Xing Hu, Peng Gu, Shuangchen Li, Yu Ji, Yuan Xie:
NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs. EMC2@HPCA/CVPR/ISCA 2019: 11-15 - [c30]Jilan Lin
CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators. ACM Great Lakes Symposium on VLSI 2019: 283-286 - [c29]Abanti Basak, Shuangchen Li, Xing Hu, Sang Min Oh, Xinfeng Xie, Li Zhao, Xiaowei Jiang, Yuan Xie:
Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads. HPCA 2019: 373-386 - [c28]Mingyu Yan, Xing Hu, Shuangchen Li, Itir Akgun, Han Li, Xin Ma, Lei Deng
Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators. ISLPED 2019: 1-6 - [c27]Wenqin Huangfu, Xueqi Li, Shuangchen Li, Xing Hu, Peng Gu, Yuan Xie:
MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm. MICRO 2019: 587-599 - [c26]Mingyu Yan, Xing Hu, Shuangchen Li, Abanti Basak, Han Li, Xin Ma, Itir Akgun, Yujing Feng, Peng Gu, Lei Deng
Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach. MICRO 2019: 615-628 - [i3]Yu Ji, Youyang Zhang, Xinfeng Xie, Shuangchen Li, Peiqi Wang, Xing Hu, Youhui Zhang, Yuan Xie:
FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture. CoRR abs/1901.09904 (2019) - [i2]Xing Hu, Ling Liang, Lei Deng, Shuangchen Li, Xinfeng Xie, Yu Ji, Yufei Ding, Chang Liu, Timothy Sherwood, Yuan Xie:
Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints. CoRR abs/1903.03916 (2019) - 2018
- [b1]Shuangchen Li:
Memory-Centric Architectures: Bridging the Gap Between Compute and Memory. University of California, Santa Barbara, USA, 2018 - [j7]Abanti Basak
Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads. IEEE Comput. Archit. Lett. 17(2): 197-200 (2018) - [j6]Mimi Xie
Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2443-2455 (2018) - [c25]Peng Gu, Dylan C. Stow, Prashansa Mukim, Shuangchen Li, Yuan Xie:
Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing. AsianHOST 2018: 74-79 - [c24]Wenqin Huangfu, Shuangchen Li, Xing Hu, Yuan Xie:
RADAR: a 3D-reRAM based DNA alignment accelerator architecture. DAC 2018: 59:1-59:6 - [c23]Mimi Xie, Shuangchen Li, Alvin Oliver Glova, Jingtong Hu, Yuangang Wang, Yuan Xie:
AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory. DATE 2018: 625-628 - [c22]Gushu Li, Guohao Dai, Shuangchen Li, Yu Wang, Yuan Xie:
GraphIA: an in-situ accelerator for large-scale graph processing. MEMSYS 2018: 79-84 - [c21]Xing Hu, Matheus Ogleari, Jishen Zhao, Shuangchen Li, Abanti Basak, Yuan Xie:
Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network. MICRO 2018: 494-506 - [c20]Shuangchen Li, Alvin Oliver Glova, Xing Hu, Peng Gu, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie:
SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator. MICRO 2018: 696-709 - [i1]Xin Ma, Liang Chang, Shuangchen Li, Lei Deng, Yufei Ding, Yuan Xie:
In-memory multiplication engine with SOT-MRAM based stochastic computing. CoRR abs/1809.08358 (2018) - 2017
- [c19]Liu Liu
Building energy-efficient multi-level cell STT-RAM caches with data compression. ASP-DAC 2017: 751-756 - [c18]Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie:
DRISA: a DRAM-based reconfigurable in-situ accelerator. MICRO 2017: 288-301 - 2016
- [j5]Kaisheng Ma
Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power. IEEE Micro 36(3): 72-83 (2016) - [j4]Daming Zhang, Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu
A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications. ACM Trans. Design Autom. Electr. Syst. 21(2): 19:1-19:32 (2016) - [c17]Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung-Hyuk Kang, Yuan Xie:
Architecture design with STT-RAM: Opportunities and challenges. ASP-DAC 2016: 109-114 - [c16]Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, Yuan Xie:
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. DAC 2016: 173:1-173:6 - [c15]Peng Gu, Shuangchen Li, Dylan C. Stow, Russell Barnes, Liu Liu
Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges. ACM Great Lakes Symposium on VLSI 2016: 347-352 - [c14]Shuangchen Li, Liu Liu
NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory. ICCAD 2016: 2 - [c13]Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie:
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. ISCA 2016: 27-39 - [c12]Yu Ji, Youhui Zhang, Shuangchen Li, Ping Chi, Cihang Jiang, Peng Qu, Yuan Xie, Wenguang Chen:
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints. MICRO 2016: 21:1-21:13 - 2015
- [j3]Kaisheng Ma
Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications. IEEE Micro 35(5): 32-40 (2015) - [c11]Shuangchen Li, Ang Li, Yongpan Liu, Yuan Xie, Huazhong Yang:
Nonvolatile memory allocation and hierarchy optimization for high-level synthesis. ASP-DAC 2015: 166-171 - [c10]Yongpan Liu, Zewei Li, Hehe Li, Yiqun Wang, Xueqing Li, Kaisheng Ma
Ambient energy harvesting nonvolatile processors: from circuit to system. DAC 2015: 150:1-150:6 - [c9]Kaisheng Ma
Architecture exploration for ambient energy harvesting nonvolatile processors. HPCA 2015: 526-537 - [c8]Shuangchen Li, Ang Li, Yuan Zhe, Yongpan Liu, Peng Li, Guangyu Sun, Yu Wang, Huazhong Yang, Yuan Xie:
Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations. ISLPED 2015: 61-66 - [c7]Shuangchen Li, Ping Chi, Jishen Zhao, Kwang-Ting Cheng
Leveraging nonvolatility for architecture design with emerging NVM. NVMSA 2015: 1-5 - 2014
- [j2]Yiqun Wang, Yongpan Liu, Shuangchen Li, Xiao Sheng, Daming Zhang, Mei-Fang Chiang, Baiko Sai, Xiaobo Sharon Hu
PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1491-1505 (2014) - [c6]Daming Zhang, Shuangchen Li, Ang Li, Yongpan Liu, Xiaobo Sharon Hu
Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes. ICCD 2014: 348-354 - 2013
- [c5]Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu
Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications. ASP-DAC 2013: 225-230 - [c4]Xinyu He, Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu, Huazhong Yang:
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications. DATE 2013: 992-995 - 2012
- [c3]Shuangchen Li, Yongpan Liu, Daming Zhang, Xinyu He, Pei Zhang, Huazhong Yang:
A hierarchical C2RTL framework for FIFO-connected stream applications. ASP-DAC 2012: 133-138 - [c2]Yiqun Wang, Yongpan Liu, Yumeng Liu, Daming Zhang, Shuangchen Li, Baiko Sai, Mei-Fang Chiang, Huazhong Yang:
A compression-based area-efficient recovery architecture for nonvolatile processors. DATE 2012: 1519-1524 - [c1]Yiqun Wang, Yongpan Liu, Shuangchen Li, Daming Zhang, Bo Zhao, Mei-Fang Chiang, Yanxin Yan, Baiko Sai, Huazhong Yang:
A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. ESSCIRC 2012: 149-152 - 2011
- [j1]Yongpan Liu, Shuangchen Li, Jue Wang, Beihua Ying, Huazhong Yang:
An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression. IEICE Trans. Electron. 94-C(7): 1220-1228 (2011)
Coauthor Index
[j16] [c52] [c51] [j15] [j14] [j13] [c48] [c47] [j12] [c44] [c43] [j11] [j10] [c42] [c41] [c40] [c39] [c38] [c37] [i4] [j9] [j8] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [i3] [i2] [j7] [j6] [c25] [c24] [c23] [c22] [c21] [c20] [i1] [c19] [c18] [j5] [c17] [c16] [c15] [c14] [c13] [c12] [j3] [c11] [c10] [c9] [c8] [c7]
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