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Christos P. Sotiriou
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2020 – today
- 2024
- [c37]Stavros Simoglou, Iordanis Lilitsis, Nikolaos Blias, Christos P. Sotiriou:
Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model. ISQED 2024: 1-8 - [c36]Christos P. Sotiriou, George Rafael Goudroumanis, Nikolaos Sketopoulos, Christos Georgakidis:
Swarm - A VLSI Timing, Fanout-aware Clustering Algorithm. ISQED 2024: 1-8 - 2023
- [c35]Christos Georgakidis, Dimitris Valiantzas, Stavros Simoglou, Iordanis Lilitsis, Nikolaos Chatzivangelis
, Ilias Golfos, Marko S. Andjelkovic, Christos P. Sotiriou, Milos Krstic
Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis. DFT 2023: 1-6 - [c34]Felipe A. Kuentzer, Christos Georgakidis, Christos P. Sotiriou, Milos Krstic
Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers. SBCCI 2023: 1-6 - 2022
- [c33]Christos Georgakidis
RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening. DFT 2022: 1-6 - [c32]Nikolaos Blias, Iordanis Lilitsis, Stavros Simoglou, Evangelos Bakas, Christos P. Sotiriou:
Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows. VLSI-SoC 2022: 1-6 - [c31]Nikolaos Chatzivangelis
Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops. VLSI-SoC 2022: 1-6 - 2021
- [j10]Osama Bin Tariq
High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs. IEEE Access 9: 54286-54297 (2021) - [j9]Kimia Zamiri Azar, Hadi Mardani Kamali
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 643-656 (2021) - [j8]Dimitrios Garyfallou
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 962-972 (2021) - [c30]Christos Georgakidis
RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints. DFT 2021: 1-6 - [c29]Stavros Simoglou, Christos P. Sotiriou, Nikolaos Blias:
Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits. DFT 2021: 1-4 - 2020
- [j7]Stavros Simoglou, Nikolaos Xiromeritis, Christos P. Sotiriou, Nikolaos Sketopoulos:
Graph-based STA for asynchronous controllers. Integr. 75: 91-101 (2020) - [c28]Stavros Simoglou, Christos P. Sotiriou, Nikolaos Blias:
Timing Errors in STA-based Gate-Level Simulation. ASYNC 2020: 1-2 - [c27]Christos Georgakidis, Christos P. Sotiriou:
Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL. DFT 2020: 1-6 - [c26]Christos Georgakidis, Georgios Ioannis Paliaroutis, Nikolaos Sketopoulos, Pelopidas Tsoumanis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis:
A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic. ISQED 2020: 231-236 - [c25]Christos Georgakidis, Christos P. Sotiriou, Nikolaos Sketopoulos, Milos Krstic
R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints. ISVLSI 2020: 316-321 - [c24]Stavros Simoglou, Christos P. Sotiriou, Dimitris Valiantzas, Nikolaos Sketopoulos:
STA for Mixed Cyclic, Acyclic Circuits. ISVLSI 2020: 392-397 - [c23]Nikolaos Sketopoulos, Christos P. Sotiriou, Vasilis F. Pavlidis:
Metal Stack and Partitioning Exploration for Monolithic 3D ICs. ISVLSI 2020: 398-403
2010 – 2019
- 2019
- [c22]Nikolaos Sketopoulos, Christos P. Sotiriou, Vasileios Samaras:
Investigation and Trade-offs in 3DIC Partitioning Methodologies: N/A. ACM Great Lakes Symposium on VLSI 2019: 451-455 - [c21]Nikolaos Xiromeritis, Stavros Simoglou, Christos P. Sotiriou, Nikolaos Sketopoulos:
Graph-Based STA for Asynchronous Controllers. PATMOS 2019: 9-16 - 2018
- [c20]Nikolaos Sketopoulos, Christos P. Sotiriou, Stavros Simoglou:
Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies. DATE 2018: 1469-1472 - 2015
- [c19]Neela Lohith Penmetsa, Christos P. Sotiriou, Sung Kyu Lim
Low Power Monolithic 3D IC Design of Asynchronous AES Core. ASYNC 2015: 93-99 - [c18]Ron Diamant, Ran Ginosar, Christos P. Sotiriou:
Asynchronous sub-threshold ultra-low power processor. PATMOS 2015: 89-96 - 2013
- [c17]Pavlos M. Mattheakis, Christos P. Sotiriou:
Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition. VLSI Design 2013: 251-256 - 2012
- [c16]Pavlos M. Mattheakis, Christos P. Sotiriou, Peter A. Beerel:
A polynomial time flow for implementing free-choice Petri-nets. ICCD 2012: 227-234 - 2011
- [j6]Qiyuan Li, Aron C. Eklund
Consistent metagenes from cancer expression profiles yield agent specific predictors of chemotherapy response. BMC Bioinform. 12: 310 (2011) - [j5]Gianluca Bontempi
Multiple-input multiple-output causal strategies for gene selection. BMC Bioinform. 12: 458 (2011) - [c15]Evriklis Kounalakis, Christos P. Sotiriou:
CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits. ASYNC 2011: 22-29 - [c14]Evriklis Kounalakis, Christos P. Sotiriou:
SCPlace: A statistical slack-assignment based constructive placer. ISQED 2011: 136-143 - [c13]Evriklis Kounalakis, Christos P. Sotiriou, Vassilis Zebilis:
Statistical Timing-Based Post-Placement Leakage Recovery. ISVLSI 2011: 102-107
2000 – 2009
- 2008
- [j4]Benjamin Haibe-Kains
A comparative study of survival models for breast cancer prognostication based on microarray data: does a single gene beat them all? Bioinform. 24(19): 2200-2208 (2008) - [p1]Benjamin Haibe-Kains
Computational Intelligence in Clinical Oncology: Lessons Learned from an Analysis of a Clinical Study. Computational Intelligence in Biomedicine and Bioinformatics 2008: 237-268 - 2007
- [c12]Nikolaos Andrikos, Luciano Lavagno, Davide Pandini, Christos P. Sotiriou:
A Fully-Automated Desynchronization Flow for Synchronous Circuits. DAC 2007: 982-985 - 2006
- [j3]Jordi Cortadella
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1904-1921 (2006) - [j2]Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou:
High Rate Data Synchronization in GALS SoCs. IEEE Trans. Very Large Scale Integr. Syst. 14(10): 1063-1074 (2006) - [c11]Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou:
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. FPL 2006: 1-6 - 2005
- [c10]Vassilis Zebilis, Christos P. Sotiriou:
Controlling Event Spacing in Self-Timed Rings. ASYNC 2005: 109-115 - 2004
- [j1]Ioannis Papaefstathiou
Design-space exploration of the most widely used cryptography algorithms. Microprocess. Microsystems 28(10): 561-571 (2004) - [c9]Ivan Blunno, Jordi Cortadella
Handshake Protocols for De-Synchronization. ASYNC 2004: 149-158 - [c8]Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou:
Data Synchronization Issues in GALS SoCs. ASYNC 2004: 170-180 - [c7]Aristides Efthymiou
Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. DATE 2004: 672-673 - [c6]Jordi Cortadella
From Synchronous to Asynchronous: An Automatic Approach. DATE 2004: 1368-1369 - [c5]Jordi Cortadella
Coping with The Variability of Combinational Logic Delays. ICCD 2004: 505-508 - 2003
- [c4]Manish Amde, Ivan Blunno, Christos P. Sotiriou:
Automating the design of an asynchronous DLX microprocessor. DAC 2003: 502-507 - [c3]Christos P. Sotiriou, Ioannis Papaefstathiou
Design-space exploration of a cryptography algorithm. ICECS 2003: 858-861 - 2002
- [c2]Christos P. Sotiriou:
Implementing asynchronous circuits using a conventional EDA tool-flow. DAC 2002: 415-418 - [c1]Ioannis Papaefstathiou
Read, use, simulate, experiment and build: an integrated approach for teaching computer architecture. WCAE 2002: 20
Coauthor Index
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