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Wang Kang 0001
Kang Wang 0001
Person information
- affiliation: Fert Beijing Institute, China
- affiliation: Beihang University, BDBC, School of Integrated Circuit Science and Engineering, School of Microelectronics, China
- affiliation (PhD 2015): University of Paris-Sud, IEF, France
Other persons with the same name
- Wang Kang — disambiguation page
- Kang Wang — disambiguation page
- Kang Wang 0002 — Rensselaer Polytechnic Institute, Department of Electrical, Computer and Systems Engineering, Troy, NY, USA
- Kang Wang 0003
— Beijing University of Technology, Faculty of Information Technology, China (and 1 more)
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2020 – today
- 2024
- [j28]Jinyu Bai
CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 189-202 (2024) - [j27]Tianshuo Bai
An End-to-End In-Memory Computing System Based on a 40-nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1729-1740 (2024) - [j26]Tsun-Yu Yang, Xiangjun Peng, Wang Kang
Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1769-1780 (2024) - [j25]Sifan Sun
CIM²PQ: An Arraywise and Hardware-Friendly Mixed Precision Quantization Method for Analog Computing-In-Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2084-2097 (2024) - [j24]Lichuan Luo
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1130-1143 (2024) - [j23]Yueting Li
Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems. ACM Trans. Embed. Comput. Syst. 23(3): 37:1-37:24 (2024) - [c53]Jinyu Bai
MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM Accelerators. ACM Great Lakes Symposium on VLSI 2024: 537-540 - 2023
- [j22]Lichuan Luo
A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 7-20 (2023) - [j21]Jinyu Bai, Wenlu Xue, Yunqian Fan, Sifan Sun, Wang Kang
Partial Sum Quantization for Computing-In-Memory-Based Neural Network Accelerator. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3049-3053 (2023) - [j20]Yueting Li
Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies. ACM Trans. Embed. Comput. Syst. 22(2): 29:1-29:24 (2023) - [j19]Yun-Shan Hsieh
Granularity-Driven Management for Reliable and Efficient Skyrmion Racetrack Memories. IEEE Trans. Emerg. Top. Comput. 11(1): 95-111 (2023) - [c52]Haiyan Qin, Yejun Zeng, Jinyu Bai, Wang Kang:
Searching Tiny Neural Networks for Deployment on Embedded FPGA. AICAS 2023: 1-5 - [c51]Syue-Wei Lu, Shuo-Han Chen, Yu-Pei Liang, Yuan-Hao Chang, Kang Wang, Tseng-Yi Chen, Wei-Kuan Shih:
Skyrmion Vault: Maximizing Skyrmion Lifespan for Enabling Low-Power Skyrmion Racetrack Memory. ASP-DAC 2023: 333-338 - [c50]Wenlu Xue, Jinyu Bai, Sifan Sun, Wang Kang:
Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement. DATE 2023: 1-6 - [c49]Yanfang Liu
OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits. ICCAD 2023: 1-9 - [c48]Jinyu Bai, Sifan Sun, Wang Kang:
Exploring Bit-Level Sparsity for Partial Sum Quantization in Computing-In-Memory Accelerator. NVMSA 2023: 32-37 - [c47]Sifan Sun, Jinming Ge, Jinyu Bai, Wang Kang:
ES-MPQ: Evolutionary Search Enabled Mixed Precision Quantization Framework for Computing-in-Memory. NVMSA 2023: 38-43 - [c46]Linjun Jiang, Sifan Sun, Jinming Ge, He Zhang, Wang Kang:
An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network. NVMSA 2023: 44-49 - [i6]Giovanni Finocchio, Supriyo Bandyopadhyay, Peng Lin, Gang Pan, J. Joshua Yang
Roadmap for Unconventional Computing with Nanotechnology. CoRR abs/2301.06727 (2023) - [i5]Yuwen Deng, Wang Kang, Wei W. Xing:
Differentiable Multi-Fidelity Fusion: Efficient Learning of Physics Simulations with Neural Architecture Search and Transfer Learning. CoRR abs/2306.06904 (2023) - 2022
- [j18]Lichuan Luo
SpinCIM: spin orbit torque memory for ternary neural networks based on the computing-in-memory architecture. CCF Trans. High Perform. Comput. 4(4): 421-434 (2022) - [j17]He Zhang
HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4465-4474 (2022) - [j16]Linjun Jiang, Erya Deng, He Zhang
A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2086-2090 (2022) - [j15]Biao Pan, Guangyao Wang
A Mini Tutorial of Processing in Memory: From Principles, Devices to Prototypes. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3044-3050 (2022) - [c45]He Zhang, Linjun Jiang, Jianxin Wu, Tingran Chen, Junzhan Liu, Wang Kang, Weisheng Zhao:
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory. DAC 2022: 109-114 - [c44]Shuo Yin, Xiang Jin, Linxu Shi, Kang Wang, Wei W. Xing
Efficient bayesian yield analysis and optimization with active learning. DAC 2022: 1195-1200 - 2021
- [c43]Jinyu Bai, Yunqian Fan, Sifan Sun, Wang Kang, Weisheng Zhao:
Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approach. A-SSCC 2021: 1-3 - [c42]Lichuan Luo
SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture. DATE 2021: 1865-1870 - [c41]He Zhang, Junzhan Liu, Kang Wang, Yunqian Fan, Shufeng Fu, Jinyu Bai, Biao Pan, Yongpan Liu, Weisheng Zhao:
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output. ICTA 2021: 123-124 - [c40]Erya Deng, Wang Kang, Weisheng Zhao, Shaoqian Wei, You Wang, Deming Zhang:
Spin-Orbit Torque Nonvolatile Flip-Flop Designs. ISCAS 2021: 1-5 - [c39]Yan Huang, Erya Deng, Jinyu Bai, Qing Yang, Wang Kang, Biao Pan:
HSC: A Hybrid Spin/CMOS Logic Based In-Memory Engine with Area-Efficient Mapping Strategy. ISCAS 2021: 1-5 - [i4]Xing Chen, Flavio Abreu Araujo, Mathieu Riou, Jacob Torrejon, Dafine Ravelosona, Wang Kang, Weisheng Zhao, Julie Grollier, Damien Querlioz:
Forecasting the outcome of spintronic experiments with Neural Ordinary Differential Equations. CoRR abs/2108.02318 (2021) - 2020
- [j14]Wang Kang
A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion. ACM J. Emerg. Technol. Comput. Syst. 16(1): 2:1-2:17 (2020) - [j13]Yun-Shan Hsieh, Po-Chun Huang
Shift-Limited Sort: Optimizing Sorting Performance on Skyrmion Memory-Based Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 4115-4128 (2020) - [c38]Haotian Wang, Wang Kang, Liuyang Zhang, He Zhang, Brajesh Kumar Kaushik
High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques. DATE 2020: 1217-1222 - [c37]He Zhang, Wang Kang, Youguang Zhang, Weisheng Zhao:
Deep Neural Network accelerator with Spintronic Memory. ACM Great Lakes Symposium on VLSI 2020: 51
2010 – 2019
- 2019
- [j12]Tinish Bhattacharya
Low-Power (1T1N) Skyrmionic Synapses for Spiking Neuromorphic Systems. IEEE Access 7: 5034-5044 (2019) - [j11]Yinglin Zhao, Peng Ouyang
An STT-MRAM Based in Memory Architecture for Low Power Integral Computing. IEEE Trans. Computers 68(4): 617-623 (2019) - [c36]Zheng Liang
ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory. DAC 2019: 158 - [c35]Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao:
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. ACM Great Lakes Symposium on VLSI 2019: 135-140 - [c34]Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Sai Li, Youguang Zhang, Weisheng Zhao:
Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface. ISCAS 2019: 1-5 - [c33]Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Youguang Zhang, Weisheng Zhao:
SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing. ISCAS 2019: 1-5 - [c32]Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao:
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. ISVLSI 2019: 203-206 - [c31]Wang Kang, He Zhang, Weisheng Zhao:
Spintronic Memories: From Memory to Computing-in-Memory. NANOARCH 2019: 1-2 - 2018
- [j10]He Zhang, Wang Kang
A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM. IEEE Access 6: 64250-64260 (2018) - [c30]He Zhang, Wang Kang, Zhaohao Wang, Erya Deng, Youguang Zhang, Weisheng Zhao:
High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory. APCCAS 2018: 382-385 - [c29]Fan Chen, Zheng Li, Wang Kang, Weisheng Zhao, Hai Li, Yiran Chen:
Process variation aware data management for magnetic skyrmions racetrack memory. ASP-DAC 2018: 221-226 - [c28]Wang Kang, Xing Chen, Daoqian Zhu, Sai Li, Yangqi Huang, Youguang Zhang, Weisheng Zhao:
Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers. DATE 2018: 119-124 - [c27]Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner
Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. ISCAS 2018: 1-5 - [c26]Bing Li, Fan Chen, Wang Kang, Weisheng Zhao, Yiran Chen, Hai Li:
Design and Data Management for Magnetic Racetrack Memory. ISCAS 2018: 1-4 - [c25]Zhaohao Wang, Zuwei Li, Yang Liu, Simin Li, Liang Chang
Progresses and challenges of spin orbit torque driven magnetization switching and application (Invited). ISCAS 2018: 1-5 - [c24]Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner
MRAM-on-FDSOI Integration: A Bit-Cell Perspective. ISVLSI 2018: 263-268 - [c23]Liuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM. ISVLSI 2018: 275-280 - [c22]Sai Li, Wang Kang, Xing Chen, Jinyu Bai, Biao Pan, Youguang Zhang, Weisheng Zhao:
Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions. ISVLSI 2018: 539-544 - [c21]Chaoxin Ding, Wang Kang, He Zhang, Youguang Zhang, Weisheng Zhao:
A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation. NANOARCH 2018: 72-78 - [c20]Wang Kang, Xing Chen, Daoqian Zhu, Xichao Zhang, Yan Zhou, Keni Qiu, Youguang Zhang, Weisheng Zhao:
A Comparative Study on Racetrack Memories: Domain Wall vs. Skyrmion. NVMSA 2018: 7-12 - [c19]Erya Deng, Zhaohao Wang, Wang Kang, Shaoqian Wei, Weisheng Zhao:
Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM. VLSI-SoC 2018: 184-187 - 2017
- [j9]Wang Kang, Liang Chang
Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective. IEEE Trans. Computers 66(3): 531-544 (2017) - [j8]Wang Kang, Tingting Pang, Weifeng Lv, Weisheng Zhao:
Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(1): 122-132 (2017) - [c18]Jiaqi Wei, Liang Chang
Ultrafast spintronic integrated circuits. ASICON 2017: 1021-1024 - [c17]Wang Kang, Liang Chang
Voltage-controlled MRAM for working memory: Perspectives and challenges. DATE 2017: 542-547 - [c16]Hao Cai, You Wang, Lirida A. B. Naviner
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device. ACM Great Lakes Symposium on VLSI 2017: 23-28 - [c15]Wang Kang, Zhaohao Wang, He Zhang, Sai Li, Youguang Zhang, Weisheng Zhao:
Advanced Low Power Spintronic Memories beyond STT-MRAM. ACM Great Lakes Symposium on VLSI 2017: 299-304 - [c14]Wang Kang, He Zhang, Peng Ouyang, Youguang Zhang, Weisheng Zhao:
Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device. ICCD 2017: 613-616 - 2016
- [j7]Yi Ran
Read disturbance issue and design techniques for nanoscale STT-MRAM. J. Syst. Archit. 71: 2-11 (2016) - [j6]Wang Kang, Yangqi Huang, Xichao Zhang
Skyrmion-Electronics: An Overview and Outlook. Proc. IEEE 104(10): 2040-2061 (2016) - [c13]Wang Kang, Tingting Pang, Bi Wu
PDS: pseudo-differential sensing scheme for STT-MRAM. DAC 2016: 120:1-120:6 - [c12]Liuyang Zhang, Aida Todri-Sanial
Quantitative evaluation of reliability and performance for STT-MRAM. ISCAS 2016: 1150-1153 - [c11]He Zhang, Wang Kang, Tingting Pang, Weifeng Lv, Youguang Zhang, Weisheng Zhao:
Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM. NANOARCH 2016: 1-6 - [c10]Liang Chang, Zhaohao Wang, Yuqian Gao, Wang Kang, Youguang Zhang, Weisheng Zhao:
Evaluation of spin-Hall-assisted STT-MRAM for cache replacement. NANOARCH 2016: 73-78 - [c9]Qian Shi, Zhaohao Wang, Yuqian Gao, Liang Chang, Wang Kang, Youguang Zhang, Weisheng Zhao:
A spin Hall effect-based multi-level cell for MRAM. NANOARCH 2016: 143-144 - [i3]Wang Kang, Yangqi Huang, Xichao Zhang, Yan Zhou, Weifeng Lv, Weisheng Zhao:
Skyrmions as Compact, Robust and Energy-Efficient Interconnects for Domain Wall (DW)-based Systems. CoRR abs/1601.03085 (2016) - [i2]Wang Kang, Chentian Zheng, Yangqi Huang, Xichao Zhang, Yan Zhou, Weifeng Lv, Weisheng Zhao:
Complementary Skyrmion Racetrack Memory with Voltage Manipulation. CoRR abs/1602.08799 (2016) - [i1]Yangqi Huang, Wang Kang, Xichao Zhang, Yan Zhou, Weisheng Zhao:
Magnetic skyrmion-based synaptic devices. CoRR abs/1608.07955 (2016) - 2015
- [j5]Wang Kang, Liuyang Zhang, Weisheng Zhao, Jacques-Olivier Klein
Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 28-39 (2015) - [j4]Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein
Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. ACM J. Emerg. Technol. Comput. Syst. 12(2): 16:1-16:42 (2015) - [j3]Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1757-1765 (2015) - [c8]Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein
Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM. ISVLSI 2015: 461-466 - [c7]Yi Ran, Wang Kang, Youguang Zhang, Jacques-Olivier Klein
Read disturbance issue for nanoscale STT-MRAM. NVMSA 2015: 1-6 - [c6]Tingting Pang, Wang Kang, Yi Ran, Youguang Zhang, Weifeng Lv, Weisheng Zhao:
Nonvolatile radiation hardened DICE latch. NVMTS 2015: 1-4 - 2014
- [j2]Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. J. Parallel Distributed Comput. 74(6): 2484-2496 (2014) - [c5]Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein
An overview of spin-based integrated circuits. ASP-DAC 2014: 676-683 - [c4]Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert:
Spintronics for low-power computing. DATE 2014: 1-6 - [c3]Zhaohao Wang, Weisheng Zhao, Wang Kang, Youguang Zhang, Jacques-Olivier Klein
Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture. IJCNN 2014: 29-34 - [c2]Wang Kang, Weisheng Zhao, Lun Yang, Jacques-Olivier Klein
One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories. NVMSA 2014: 1-6 - 2013
- [j1]Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. Microelectron. Reliab. 53(9-11): 1224-1229 (2013) - 2012
- [c1]Wang Kang, Youguang Zhang, Mingbang Wang, Guoyan Li:
Improving flash memory reliability with dynamic thresholds: Signal processing and coding schemes. CHINACOM 2012: 161-166
Coauthor Index
[j28] [j25] [j23] [j20] [j16] [j15] [c45] [c43] [c42] [c41] [c40] [i4] [j14] [c38] [c37] [j12] [j11] [c36] [c35] [c34] [c33] [c32] [c31] [j10] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [j9] [j8] [c18] [c17] [c16] [c15] [c14] [j7] [j6] [c13] [c12] [c11] [c10] [c9] [i3] [i2] [i1] [j5] [j4] [j3] [c8] [c7] [c6] [j2] [c5] [c4] [c3] [c2] [j1]
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