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Alexandre Levisse
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2020 – today
- 2024
- [j13]Rafael Medina, Giovanni Ansaloni, Marina Zapater, Alexandre Levisse, Saeideh Alinezhad Chamazcoti, Timon Evenblij, Dwaipayan Biswas, Francky Catthoor, David Atienza:
Bank on Compute-Near-Memory: Design Space Exploration of Processing-Near-Bank Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 4117-4129 (2024) - [j12]Pengbo Yu
, Flavio Ponzina
An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1018-1031 (2024) - [c26]Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor:
DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD. ISVLSI 2024: 204-209 - [i5]Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza:
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. CoRR abs/2406.14263 (2024) - 2023
- [j11]Silvio Zanoli
An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(2): 489-501 (2023) - [j10]Joshua Klein
ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning. IEEE Trans. Computers 72(7): 1985-1998 (2023) - [j9]Halima Najibi, Alexandre Levisse
Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 2-15 (2023) - [j8]Flavio Ponzina
Overflow-free Compute Memories for Edge AI Acceleration. ACM Trans. Embed. Comput. Syst. 22(5s): 121:1-121:23 (2023) - [j7]Marco Rios
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. IEEE Trans. Emerg. Top. Comput. 11(2): 358-372 (2023) - [j6]Sergi Abadal, Robert Guirado, Hamidreza Taghvaee
Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors. IEEE Wirel. Commun. 30(4): 162-169 (2023) - 2022
- [j5]Flavio Ponzina
A Hardware/Software Co-Design Vision for Deep Learning at the Edge. IEEE Micro 42(6): 48-54 (2022) - [c25]Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza:
Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays. ACM Great Lakes Symposium on VLSI 2022: 223-228 - [c24]Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. ACM Great Lakes Symposium on VLSI 2022: 249-254 - [i4]Joshua Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza:
ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning. CoRR abs/2205.10042 (2022) - [i3]Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza:
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. CoRR abs/2209.06108 (2022) - [i2]Pengbo Yu, Alexandre Levisse, Mohit Gupta, Timon Evenblij, Giovanni Ansaloni, Francky Catthoor, David Atienza:
A Soft SIMD Based Energy Efficient Computing Microarchitecture. CoRR abs/2212.09358 (2022) - 2021
- [c23]Joshua Klein, Alexandre Levisse, Giovanni Ansaloni, David Atienza, Marina Zapater, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH). CF 2021: 191-193 - [c22]William Andrew Simon, Valérian Ray
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding. DAC 2021: 805-810 - [c21]Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. DATE 2021: 1881-1886 - [c20]Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. ISVLSI 2021: 164-169 - 2020
- [j4]Alexandre Levisse
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations. IEEE Access 8: 109297-109308 (2020) - [j3]William Andrew Simon
BLADE: An in-Cache Computing Architecture for Edge Devices. IEEE Trans. Computers 69(9): 1349-1363 (2020) - [j2]Loris Duch
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2122-2133 (2020) - [c19]Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza:
RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures. ASP-DAC 2020: 181-186 - [c18]Halima Najibi, Alexandre Levisse, Marina Zapater, Mohamed M. Sabry Aly, David Atienza:
Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology. ACM Great Lakes Symposium on VLSI 2020: 513-518 - [c17]Alexandre Levisse, Marco Rios, Miguel Peón Quirós, David Atienza:
Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. ICASSP 2020: 1549-1552 - [c16]Halima Najibi, Jorge Hunter, Alexandre Levisse, Marina Zapater, Miroslav Vasic, David Atienza:
Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters. ISVLSI 2020: 18-23 - [c15]William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza:
A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance. VLSI-SOC 2020: 94-99 - [i1]Sergi Abadal, Robert Guirado
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors. CoRR abs/2011.04107 (2020)
2010 – 2019
- 2019
- [j1]Mouhamad Alayan
Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 748-752 (2019) - [c14]William Andrew Simon, Juan Galicia, Alexandre Levisse, Marina Zapater, David Atienza:
A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture. DAC 2019: 83 - [c13]William Andrew Simon, Yasir Mahmood Qureshi, Alexandre Levisse, Marina Zapater, David Atienza:
BLADE: A BitLine Accelerator for Devices on the Edge. ACM Great Lakes Symposium on VLSI 2019: 207-212 - [c12]Halima Najibi, Alexandre Levisse, Marina Zapater:
A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays. ISLPED 2019: 1-6 - [c11]Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza:
Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS 2019: 1-4 - [c10]Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet
RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. SAMOS 2019: 34-47 - [c9]Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza:
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication. VLSI-SoC 2019: 34-39 - 2018
- [c8]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau
RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. DCIS 2018: 1-6 - [c7]Gilbert Sassine, Cecile Nail, Luc Tillie, Diego Alfaro Robayo, Alexandre Levisse, Carlo Cagli, Khalil El Hajjam, Jean-Francois Nodin, Elisa Vianello, Mathieu Bernard, Gabriel Molas, Etienne Nowak
Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications. IRPS 2018: 2-1 - 2017
- [c6]Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon:
Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS 2017: 1-4 - [c5]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau
High density emerging resistive memories: What are the limits? LASCAS 2017: 1-4 - [c4]Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau
Architecture, design and technology guidelines for crosspoint memories. NANOARCH 2017: 55-60 - 2016
- [c3]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. NANOARCH 2016: 7-12 - 2015
- [c2]Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. NVMTS 2015: 1-4 - 2014
- [c1]S. Ben Krit, Wenceslas Rahajandraibe, Karine Castellani-Coulié, Gilles Micolau, Alexandre Levisse, A. Lyoussi:
Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination. LATW 2014: 1-6
Coauthor Index
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