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Threats on Logic Locking: A Decade Later

Published: 13 May 2019 Publication History

Abstract

To reduce the cost of ICs and to meet the market's demand, a considerable portion of manufacturing supply chain, including silicon fabrication, packaging and testing may be pushed offshore. Utilizing a global IC manufacturing supply chain, and inclusion of non-trusted parties in the supply chain has raised concerns over security and trust related challenges including those of overproduction, counterfeiting, IP piracy, and Hardware Trojans to name a few. To reduce the risk of IC manufacturing in an untrusted and globally distributed supply chain, the researchers have proposed various locking and obfuscation mechanisms for hiding the functionality of the ICs during the manufacturing, that requires the activation of the IP after fabrication using the key value(s) that is only known to the IP/IC owner. At the same time, many such proposed obfuscation and locking mechanisms are broken with attacks that exploit the inherent vulnerabilities in such solutions. The past decade of research in this area, has resulted in many such defense and attack solutions. In this paper, we review a decade of research on hardware obfuscation from an attacker perspective, elaborate on attack and defense lessons learned, and discuss future directions that could be exploited for building stronger defenses.

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Cited By

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  • (2024)Automated Hardware Security Evaluation Framework Using PSO and CNN for Optimizing Key Gate Placement and Enhanced Security Analysis2024 International Conference on Emerging Techniques in Computational Intelligence (ICETCI)10.1109/ICETCI62771.2024.10704194(418-425)Online publication date: 22-Aug-2024
  • (2024)Quantifiable Assurance in HardwareHardware Security10.1007/978-3-031-58687-3_1(1-52)Online publication date: 3-Apr-2024
  • (2023)CENSOR: Privacy-preserving Obfuscation for Outsourcing SAT formulas2023 IEEE 22nd International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom)10.1109/TrustCom60117.2023.00147(1060-1067)Online publication date: 1-Nov-2023
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cover image ACM Conferences
GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI
May 2019
562 pages
ISBN:9781450362528
DOI:10.1145/3299874
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 13 May 2019

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Author Tags

  1. logic locking
  2. reverse engineering
  3. sat attack
  4. smt attack

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GLSVLSI '19
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GLSVLSI '19: Great Lakes Symposium on VLSI 2019
May 9 - 11, 2019
VA, Tysons Corner, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2024)Automated Hardware Security Evaluation Framework Using PSO and CNN for Optimizing Key Gate Placement and Enhanced Security Analysis2024 International Conference on Emerging Techniques in Computational Intelligence (ICETCI)10.1109/ICETCI62771.2024.10704194(418-425)Online publication date: 22-Aug-2024
  • (2024)Quantifiable Assurance in HardwareHardware Security10.1007/978-3-031-58687-3_1(1-52)Online publication date: 3-Apr-2024
  • (2023)CENSOR: Privacy-preserving Obfuscation for Outsourcing SAT formulas2023 IEEE 22nd International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom)10.1109/TrustCom60117.2023.00147(1060-1067)Online publication date: 1-Nov-2023
  • (2023)IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering AttacksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333731032:2(347-360)Online publication date: 12-Dec-2023
  • (2023)Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon DemonstrationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322384642:7(2094-2107)Online publication date: 1-Jul-2023
  • (2023)Impact of Satisfiability Solvers on Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_7(131-154)Online publication date: 23-Sep-2023
  • (2023)Fundamentals of Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_5(89-107)Online publication date: 26-Jun-2023
  • (2023)Optical Probing Attack on Logic LockingHardware Security Training, Hands-on!10.1007/978-3-031-31034-8_14(259-271)Online publication date: 30-Jun-2023
  • (2022)A Neural Network-Based Cognitive Obfuscation Toward Enhanced Logic LockingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313868641:11(4587-4599)Online publication date: 1-Nov-2022
  • (2022)Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning AttacksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310027541:6(1716-1729)Online publication date: Jun-2022
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