Abstract
No abstract available.
Cited By
- Chasapis D, Vavouliotis G, Jiménez D and Casas M Instruction-Aware Cooperative TLB and Cache Replacement Policies Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1, (619-636)
- Christou N, Gaidis A, Atlidakis V and Kemerlis V Eclipse: Preventing Speculative Memory-error Abuse with Artificial Data Dependencies Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, (3913-3927)
- Rosa L, Foschini L and Corradi A (2024). Empowering Cloud Computing With Network Acceleration: A Survey, IEEE Communications Surveys & Tutorials, 26:4, (2729-2768), Online publication date: 1-Oct-2024.
- Jin D, Gaidis A and Kemerlis V BeeBox Proceedings of the 33rd USENIX Conference on Security Symposium, (613-630)
- Liu T, Guo J and Huang B (2023). Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping, ACM Transactions on Architecture and Code Optimization, 21:1, (1-26), Online publication date: 31-Mar-2024.
- Palanivelu S, Radhakrishnan S, Chandrasekaran K, Barua S and Fayek H (2023). Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices, IET Communications, 17:11, (1310-1320), Online publication date: 3-Jul-2023.
- Yip E, Girault A, Roop P and Biglari-Abhari M (2023). Synchronous Deterministic Parallel Programming for Multi-Cores with ForeC, ACM Transactions on Programming Languages and Systems, 45:2, (1-74), Online publication date: 30-Jun-2023.
- Zhang S, Naderan-Tahan M, Jahre M and Eeckhout L SAC: Sharing-Aware Caching in Multi-Chip GPUs Proceedings of the 50th Annual International Symposium on Computer Architecture, (1-13)
- Su Z, Wang D, Yu Z, Yang Y, Jiang Y, Wang R, Chang W, Li W, Cui A and Sun J (2023). PHCG: Optimizing Simulink Code Generation for Embedded System With SIMD Instructions, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42:4, (1072-1084), Online publication date: 1-Apr-2023.
- AlJame M, Alnoori A, Alfailakawi M and Ahmad I (2023). A Spark-Based Parallel Implementation of Arithmetic Optimization Algorithm, International Journal of Applied Metaheuristic Computing, 14:1, (1-27), Online publication date: 24-Feb-2023.
- Vagelatos A and Sarivougioukas J (2021). Fused Contextual Data With Threading Technology to Accelerate Processing in Home UbiHealth, International Journal of Software Science and Computational Intelligence, 14:1, (1-14), Online publication date: 25-Oct-2022.
- Goswami K, Das S, Satapathy S and Banerjee D A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices Proceedings of the 2022 International Symposium on Memory Systems, (1-16)
- Vavouliotis G, Chacon G, Alvarez L, Gratz P, Jiménez D and Casas M Page Size Aware Cache Prefetching Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture, (956-974)
- Miao C, Bu K, Li M, Mao S and Jia J SwiftDir: Secure Cache Coherence without Overprotection Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture, (662-677)
- McAllister S, Berg B, Tutuncu-Macias J, Yang J, Gunasekar S, Lu J, Berger D, Beckmann N and Ganger G (2022). Kangaroo: Theory and Practice of Caching Billions of Tiny Objects on Flash, ACM Transactions on Storage, 18:3, (1-33), Online publication date: 31-Aug-2022.
- Xia Z, Cui Y, Zhang A, Zhang P, Long S, Tang T, Peng L, Huang C, Yang C and Liao X Large-Scale Parallel Alignment Algorithm for SMRT Reads Algorithms and Architectures for Parallel Processing, (213-229)
- McAllister S, Berg B, Tutuncu-Macias J, Yang J, Gunasekar S, Lu J, Berger D, Beckmann N and Ganger G Kangaroo Proceedings of the ACM SIGOPS 28th Symposium on Operating Systems Principles, (243-262)
- Vavouliotis G, Alvarez L, Grot B, Jiménez D and Casas M Morrigan: A Composite Instruction TLB Prefetcher MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, (1138-1153)
- Du X and Li C Predicting Uncorrectable Memory Errors from the Correctable Error History: No Free Predictors in the Field Proceedings of the International Symposium on Memory Systems, (1-10)
- Vavouliotis G, Alvarez L, Karakostas V, Nikas K, Koziris N, Jiménez D and Casas M Exploiting page table locality for agile TLB prefetching Proceedings of the 48th Annual International Symposium on Computer Architecture, (85-98)
- Abts D, Ross J, Sparling J, Wong-VanHaren M, Baker M, Hawkins T, Bell A, Thompson J, Kahsai T, Kimmell G, Hwang J, Leslie-Hurd R, Bye M, Creswick E, Boyd M, Venigalla M, Laforge E, Purdy J, Kamath P, Maheshwari D, Beidler M, Rosseel G, Ahmad O, Gagarin G, Czekalski R, Rane A, Parmar S, Werner J, Sproch J, Macias A and Kurtz B Think fast Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture, (145-158)
- Kurth A, Wolters K, Forsberg B, Capotondi A, Marongiu A, Grosser T and Benini L Mixed-data-model heterogeneous compilation and OpenMP offloading Proceedings of the 29th International Conference on Compiler Construction, (119-131)
- Zahran M and Berger M Parallel Computing At The Undergraduate Level Proceedings of the Workshop on Computer Architecture Education, (1-7)
- Cabodi G, Camurati P, Finocchiaro F and Vendraminetto D Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification Codes, Cryptology and Information Security, (462-479)
- Leet C, Chen S, Gao K and Yang Y Precedence Proceedings of the 2019 ACM Symposium on SDN Research, (1-7)
- García J and Carriegos M (2019). On parallel computation of centrality measures of graphs, The Journal of Supercomputing, 75:3, (1410-1428), Online publication date: 1-Mar-2019.
- Hennessy J and Patterson D (2019). A new golden age for computer architecture, Communications of the ACM, 62:2, (48-60), Online publication date: 28-Jan-2019.
- Forsell M, Roivainen J and Leppänen V (2018). REPLICA MBTAC, The Journal of Supercomputing, 74:5, (1911-1933), Online publication date: 1-May-2018.
- Deshpande A and Draper J A New Metric to Measure Cache Utilization for HPC Workloads Proceedings of the Second International Symposium on Memory Systems, (10-17)
- Caheny P, Casas M, Moretó M, Gloaguen H, Saintes M, Ayguadé E, Labarta J and Valero M Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, (275-286)
- Agarwal M and Jailia M Effect of TLB on system performance Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies, (1-4)
- Shidal J, Spilo A, Scheid P, Cytron R and Kavi K (2015). Recycling trash in cache, ACM SIGPLAN Notices, 50:11, (118-130), Online publication date: 28-Jan-2016.
- Deshpande A and Draper J Modeling Data Movement in the Memory Hierarchy in HPC Systems Proceedings of the 2015 International Symposium on Memory Systems, (158-161)
- Chatzigeorgiou A, Chaikalis T, Paschalidou G, Vesyropoulos N, Georgiadis C and Stiakakis E A Taxonomy of Evaluation Approaches in Software Engineering Proceedings of the 7th Balkan Conference on Informatics Conference, (1-8)
- Hetherington T, O'Connor M and Aamodt T MemcachedGPU Proceedings of the Sixth ACM Symposium on Cloud Computing, (43-57)
- Shidal J, Spilo A, Scheid P, Cytron R and Kavi K Recycling trash in cache Proceedings of the 2015 International Symposium on Memory Management, (118-130)
- Patterson D (2012). For better or worse, benchmarks shape a field, Communications of the ACM, 55:7, (104-104), Online publication date: 1-Jul-2012.
- Galceran-Oms M, Gotmanov A, Cortadella J and Kishinevsky M (2011). Microarchitectural Transformations Using Elasticity, ACM Journal on Emerging Technologies in Computing Systems, 7:4, (1-24), Online publication date: 1-Dec-2011.
- Kramer W How to measure useful, sustained performance State of the Practice Reports, (1-18)
- Rahman M A combined arithmetic logic unit and memory element for the design of a parallel computer Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I, (306-317)
- Posadas H, Díaz L and Villar E Fast data-cache modeling for native co-simulation Proceedings of the 16th Asia and South Pacific Design Automation Conference, (425-430)
- Balasubramanian P, Prasad K and Mastorakis N (2010). A standard cell based synchronous dual-bit adder with embedded carry look-ahead, WSEAS Transactions on Circuits and Systems, 9:12, (736-745), Online publication date: 1-Dec-2010.
- Balasubramanian P, Prasad K and Mastorakis N A standard cell based synchronous dual-bit adder with embedded carry look-ahead Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science, (175-182)
- Lee E and Seshia S An introductory textbook on cyber-physical systems Proceedings of the 2010 Workshop on Embedded Systems Education, (1-6)
- Palem K Compilers, architectures and synthesis for embedded computing Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems, (167-176)
- Elastic systems Proceedings of the Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign, (149-158)
- Liao G, Yu H and Bhuyan L A new IP lookup cache for high performance IP routers Proceedings of the 47th Design Automation Conference, (338-343)
- Nurvitadhi E, Hoe J, Kam T and Lu S Automatic pipelining from transactional datapath specifications Proceedings of the Conference on Design, Automation and Test in Europe, (1001-1004)
- Galceran-Oms M, Cortadella J, Bufistov D and Kishinevsky M Automatic microarchitectural pipelining Proceedings of the Conference on Design, Automation and Test in Europe, (961-964)
- Yu H A memory- and time-efficient on-chip TCAM minimizer for IP lookup Proceedings of the Conference on Design, Automation and Test in Europe, (926-931)
- Carmona J, Cortadella J, Kishinevsky M and Taubin A (2009). Elastic circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28:10, (1437-1455), Online publication date: 1-Oct-2009.
- Bartzas A, Peon-Quiros M, Mamagkakis S, Catthoor_affcnd F, Soudris D and Mendias J (2009). Direct memory access usage optimization in network applications for reduced memory latency and energy consumption, Journal of Embedded Computing, 3:3, (241-254), Online publication date: 1-Aug-2009.
- Kejariwal A, Nicolau A, Banerjee U, Veidenbaum A and Polychronopoulos C Cache-aware partitioning of multi-dimensional iteration spaces Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference, (1-12)
- Nagarajan V and Gupta R Architectural support for shadow memory in multiprocessors Proceedings of the 2009 ACM SIGPLAN/SIGOPS international conference on Virtual execution environments, (1-10)
- Chevallier R, Encrenaz-Tiphene E, Fribourg L and Xu W (2009). Timed verification of the generic architecture of a memory circuit using parametric timed automata, Formal Methods in System Design, 34:1, (59-81), Online publication date: 1-Feb-2009.
- Yu Z and Baas B (2009). High performance, energy efficiency, and scalability with GALS chip multiprocessors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17:1, (66-79), Online publication date: 1-Jan-2009.
- Kam T, Kishinevsky M, Cortadella J and Galceran-Oms M Correct-by-construction microarchitectural pipelining Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, (434-441)
- Huang Y, Zhang W and Zang B Undergraduate education in the computer system of software school, Fudan University Proceedings of the 1st ACM Summit on Computing Education in China on First ACM Summit on Computing Education in China, (1-3)
- Reuter A (2008). Is there life outside transactions?, ACM SIGMOD Record, 37:2, (54-58), Online publication date: 1-Jun-2008.
- Biggar P, Nash N, Williams K and Gregg D (2008). An experimental study of sorting and branch prediction, ACM Journal of Experimental Algorithmics, 12, (1-39), Online publication date: 1-Jun-2008.
- Directed-Logical Testing for Functional Verification of Microprocessors Proceedings of the Sixth ACM/IEEE International Conference on Formal Methods and Models for Co-Design, (89-100)
- Mishra P and Dutt N (2008). Processor Description Languages, 10.5555/1481522, Online publication date: 29-May-2008.
- Kejariwal A, Nicolau A, Banerjee U, Veidenbaum A and Polychronopoulos C Cache-aware iteration space partitioning Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, (269-270)
- Bartzas A, Peon-Quiros M, Mamagkakis S, Catthoor F, Soudris D and Mendias J Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information Proceedings of the 2008 Asia and South Pacific Design Automation Conference, (434-439)
- Blumer A and Patterson C (2008). Exploiting process locality of reference in RTL simulation acceleration, EURASIP Journal on Embedded Systems, 2008, (1-10), Online publication date: 1-Jan-2008.
- Grabher P, Großschädl J and Page D Cryptographic side-channels from low-power cache memory Proceedings of the 11th IMA international conference on Cryptography and coding, (170-184)
- Aciiçmez O Yet another MicroArchitectural Attack: Proceedings of the 2007 ACM workshop on Computer security architecture, (11-18)
- Iwato H, Sakanushi K, Takeuchi Y and Imai M A low power VLIW processor generation method by means of extracting non-redundant activation conditions Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, (227-232)
- Peon-Quiros M, Bartzas A, Mamagkakis S, Catthoor F, Mendias J and Soudris D Direct memory access optimization in wireless terminals for reduced memory latency and energy consumption Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation, (373-383)
- Cheveresan R, Ramsay M, Feucht C and Sharapov I Characteristics of workloads used in high performance and technical computing Proceedings of the 21st annual international conference on Supercomputing, (73-82)
- Bečvář M and Kahánek S VLIW-DLX simulator for educational purposes Proceedings of the 2007 workshop on Computer architecture education, (8-13)
- Andrikos N, Lavagno L, Pandini D and Sotiriou C A fully-automated desynchronization flow for synchronous circuits Proceedings of the 44th annual Design Automation Conference, (982-985)
- Zhu Q, Shrivastava A and Dutt N Interactive presentation: Functional and timing validation of partially bypassed processor pipelines Proceedings of the conference on Design, automation and test in Europe, (1164-1169)
- Aciiçmez O, Koç Ç and Seifert J On the power of simple branch prediction analysis Proceedings of the 2nd ACM symposium on Information, computer and communications security, (312-320)
- Robinson A and Garside J Sensitive registers Proceedings of the 17th ACM Great Lakes symposium on VLSI, (138-143)
- Radhakrishnan S, Chinthamani S and Cheng K (2007). The Blackford Northbridge Chipset for the Intel 5000, IEEE Micro, 27:2, (22-33), Online publication date: 1-Mar-2007.
- Taubin A, Cortadella J, Lavagno L, Kondratyev A and Peeters A (2007). Design automation of real-life asynchronous devices and systems, Foundations and Trends in Electronic Design Automation, 2:1, (1-133), Online publication date: 1-Jan-2007.
- Anckaert B, Jakubowski M and Venkatesan R Proteus Proceedings of the ACM workshop on Digital rights management, (47-58)
- Citron D, Hurani A and Gnadrey A (2006). The harmonic or geometric mean, ACM SIGARCH Computer Architecture News, 34:4, (18-25), Online publication date: 1-Sep-2006.
- Shrivastava A, Earlie E, Dutt N and Nicolau A (2006). Retargetable pipeline hazard detection for partially bypassed processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14:8, (791-801), Online publication date: 1-Aug-2006.
- Cortadella J, Kishinevsky M and Grundmann B Synthesis of synchronous elastic architectures Proceedings of the 43rd annual Design Automation Conference, (657-662)
- Xie Y, Wolf W and Lekatsas H (2006). Code compression for embedded VLIW processors using variable-to-fixed coding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14:5, (525-536), Online publication date: 1-May-2006.
- Tay Y and Zou M (2006). A page fault equation for modeling the effect of memory size, Performance Evaluation, 63:2, (99-130), Online publication date: 1-Feb-2006.
- Andraus Z, Liffiton M and Sakallah K Refinement strategies for verification methods based on datapath abstraction Proceedings of the 2006 Asia and South Pacific Design Automation Conference, (19-24)
- Weinberg J, McCracken M, Strohmaier E and Snavely A Quantifying Locality In The Memory Access Patterns of HPC Applications Proceedings of the 2005 ACM/IEEE conference on Supercomputing
- Ge R, Feng X and Cameron K Performance-constrained Distributed DVS Scheduling for Scientific Applications on Power-aware Clusters Proceedings of the 2005 ACM/IEEE conference on Supercomputing
- Ge J, Chaudhuri S and Tyagi A Control flow based obfuscation Proceedings of the 5th ACM workshop on Digital rights management, (83-92)
- Barabash K, Ben-Yitzhak O, Goft I, Kolodner E, Leikehman V, Ossia Y, Owshanko A and Petrank E (2005). A parallel, incremental, mostly concurrent garbage collector for servers, ACM Transactions on Programming Languages and Systems, 27:6, (1097-1146), Online publication date: 1-Nov-2005.
- Babot F, Bertran M and Climent A A static communication elimination algorithm for distributed system verification Proceedings of the 7th international conference on Formal Methods and Software Engineering, (375-389)
- Yotov K, Jackson S, Steele T, Pingali K and Stodghill P Automatic measurement of instruction cache capacity Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing, (230-243)
- Gordon-Ross A and Vahid F (2005). Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware, IEEE Transactions on Computers, 54:10, (1203-1215), Online publication date: 1-Oct-2005.
- Liu Y and Furber S The design of an asynchronous carry-lookahead adder based on data characteristics Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (647-656)
- Ishii N, Ogi H, Mochizuki T and Iwata K Parallelism improvements of software pipelining by combining spilling with rematerialization Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I, (820-826)
- Kim S and Chae S Complexity reduction in an nRERL microprocessor Proceedings of the 2005 international symposium on Low power electronics and design, (180-185)
- Kim H and Kim T Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse Proceedings of the 42nd annual Design Automation Conference, (341-344)
- Yotov K, Pingali K and Stodghill P (2005). Automatic measurement of memory hierarchy parameters, ACM SIGMETRICS Performance Evaluation Review, 33:1, (181-192), Online publication date: 6-Jun-2005.
- Yotov K, Pingali K and Stodghill P Automatic measurement of memory hierarchy parameters Proceedings of the 2005 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, (181-192)
- Khouri K, Lakshminarayana G and Jha N (2005). Memory binding for performance optimization of control-flow intensive behavioral descriptions, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13:5, (513-524), Online publication date: 1-May-2005.
- Feng X, Ge R and Cameron K Power and Energy Profiling of Scientific Applications on Distributed Systems Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
- Nalabalapu P and Sass R Bandwidth Management with a Reconfigurable Data Cache Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
- McCorkle E Programmable bus/memory controllers in modern computer architecture Proceedings of the 43rd annual ACM Southeast Conference - Volume 1, (194-199)
- Ishihara T and Fallah F A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors Proceedings of the conference on Design, Automation and Test in Europe - Volume 1, (358-363)
- Shrivastava A, Dutt N, Nicolau A and Earlie E PBExplore Proceedings of the conference on Design, Automation and Test in Europe - Volume 2, (1264-1269)
- Mishra P and Dutt N Functional Coverage Driven Test Generation for Validation of Pipelined Processors Proceedings of the conference on Design, Automation and Test in Europe - Volume 2, (678-683)
- Lysaght P and Subrahmanyam P (2005). Guest Editors' Introduction, IEEE Design & Test, 22:2, (85-89), Online publication date: 1-Mar-2005.
- Uht A (2005). Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control, IEEE Transactions on Computers, 54:2, (132-140), Online publication date: 1-Feb-2005.
- Cheung N, Parameswaran S and Henkel J Battery-aware instruction generation for embedded processors Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (553-556)
- Bouyssounouse B and Sifakis J Low power engineering Embedded Systems Design, (450-478)
- Ko I and Leem C (2004). An Improvement of Response Speed for Electronic Commerce Systems, Information Systems Frontiers, 6:4, (313-323), Online publication date: 1-Dec-2004.
- Shrivastava A, Earlie E, Dutt N and Nicolau A Operation tables for scheduling in the presence of incomplete bypassing Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (194-199)
- Wang W, Raghunathan A, Lakshminarayana G and Jha N (2004). Input space adaptive design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12:6, (590-602), Online publication date: 1-Jun-2004.
- Ashok R, Chheda S and Moritz C (2004). Coupling compiler-enabled and conventional memory accessing for energy efficiency, ACM Transactions on Computer Systems, 22:2, (180-213), Online publication date: 1-May-2004.
- McKee S Reflections on the memory wall Proceedings of the 1st conference on Computing frontiers
- Mishra P, Dutt N, Krishnamurthy N and Abadir M (2004). A Top-Down Methodology for Microprocessor Validation, IEEE Design & Test, 21:2, (122-131), Online publication date: 1-Mar-2004.
- Mishra P and Dutt N Graph-Based Functional Test Program Generation for Pipelined Processors Proceedings of the conference on Design, automation and test in Europe - Volume 1
- Mishra P and Dutt N (2004). Modeling and validation of pipeline specifications, ACM Transactions on Embedded Computing Systems, 3:1, (114-139), Online publication date: 1-Feb-2004.
- Togawa N, Tachikake K, Miyaoka Y, Yanagisawa M and Ohtsuki T Instruction set and functional unit synthesis for SIMD processor cores Proceedings of the 2004 Asia and South Pacific Design Automation Conference, (743-750)
- Formal verification of pipelined processors with precise exceptions Proceedings of the Second ACM/IEEE International Conference on Formal Methods and Models for Co-Design, (129-139)
- Barabash K, Ossia Y and Petrank E (2003). Mostly concurrent garbage collection revisited, ACM SIGPLAN Notices, 38:11, (255-268), Online publication date: 26-Nov-2003.
- Liu J, Zhou S, Zhu H and Cheng C An Algorithmic Approach for Generic Parallel Adders Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
- Park I, Kang S and Yi Y Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
- Hanson F (2003). Local supercomputing training in the computational sciences using remote national centers, Future Generation Computer Systems, 19:8, (1335-1347), Online publication date: 1-Nov-2003.
- Gordon-Ross A and Vahid F Frequent loop detection using efficient non-intrusive on-chip hardware Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, (117-124)
- Barabash K, Ossia Y and Petrank E Mostly concurrent garbage collection revisited Proceedings of the 18th annual ACM SIGPLAN conference on Object-oriented programing, systems, languages, and applications, (255-268)
- Kumar R, Tsiatsis V and Srivastava M Computation hierarchy for in-network processing Proceedings of the 2nd ACM international conference on Wireless sensor networks and applications, (68-77)
- Hosabettu R, Gopalakrishnan G and Srivas M (2003). Formal Verification of a Complex Pipelined Processor, Formal Methods in System Design, 23:2, (171-213), Online publication date: 1-Sep-2003.
- Memik G, Reinman G and Mangione-Smith W Reducing energy and delay using efficient victim caches Proceedings of the 2003 international symposium on Low power electronics and design, (262-265)
- Sequeira K, Zaki M, Szymanski B and Carothers C Improving spatial locality of programs via data mining Proceedings of the ninth ACM SIGKDD international conference on Knowledge discovery and data mining, (649-654)
- Azimi R and Bilas A miNI Proceedings of the 17th annual international conference on Supercomputing, (261-272)
- Amde M, Blunno I and Sotiriou C Automating the design of an asynchronous DLX microprocessor Proceedings of the 40th annual Design Automation Conference, (502-507)
- Mishra P, Dutt N and Tomiyama H (2003). Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications, Design Automation for Embedded Systems, 8:2-3, (249-265), Online publication date: 1-Jun-2003.
- Stephenson M, O'Reilly U, Martin M and Amarasinghe S Genetic programming applied to compiler heuristic optimization Proceedings of the 6th European conference on Genetic programming, (238-253)
- Baray F, Codognet P, Diaz D and Michel H Code-based test generation for validation of functional processor descriptions Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems, (569-584)
- Dramaliev I and Madhyastha T Optimizing probe-based storage Proceedings of the 2nd USENIX conference on File and storage technologies, (8-8)
- Xie Y, Wolf W and Lekatsas H Profile-Driven Selective Code Compression Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
- Lodi A, Toma M and Campi F A pipelined configurable gate array for embedded processors Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, (21-30)
- Memik G, Reinman G and Mangione-Smith W Just Say No Proceedings of the 9th International Symposium on High-Performance Computer Architecture
- Tachikake K, Togawa N, Miyaoka Y, Choi J, Yanagisawa M and Ohtsuki T A hardware/software partitioning algorithm for SIMD processor cores Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (135-140)
- Verma M, Steinke S and Marwedel P Data partitioning for maximal scratchpad usage Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (77-83)
- Dongarra J, Foster I, Fox G, Gropp W, Kennedy K, Torczon L and White A References Sourcebook of parallel computing, (729-789)
- Quinn M, Miller R, Miller R and Quinn M Parallel processing Encyclopedia of Computer Science, (1349-1365)
- Frailey D Computer architecture Encyclopedia of Computer Science, (304-319)
- Ashok R, Chheda S and Moritz C (2002). Cool-Mem, ACM SIGOPS Operating Systems Review, 36:5, (133-143), Online publication date: 1-Dec-2002.
- Ashok R, Chheda S and Moritz C (2002). Cool-Mem, ACM SIGARCH Computer Architecture News, 30:5, (133-143), Online publication date: 1-Dec-2002.
- Park I, Powell M and Vijaykumar T Reducing register ports for higher speed and lower energy Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, (171-182)
- Sun F, Ravi S, Raghunathan A and Jha N Synthesis of custom processors based on extensible platforms Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, (641-648)
- Radinger W and Goeschka K A definition of convergence in the area of information and telecommunication technologies Companion of the 17th annual ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications, (88-89)
- Smith J (2002). The influence of ATM on operating systems, ACM SIGCOMM Computer Communication Review, 32:5, (29-37), Online publication date: 1-Nov-2002.
- Paulin P, Pilkington C and Bensoudane E (2002). StepNP, IEEE Design & Test, 19:6, (17-26), Online publication date: 1-Nov-2002.
- Malik A, Moyer B and Zhou R Embedded cache architecture with programmable write buffer support for power and performance flexibility Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, (98-107)
- Ashok R, Chheda S and Moritz C Cool-Mem Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, (133-143)
- Ashok R, Chheda S and Moritz C (2002). Cool-Mem, ACM SIGPLAN Notices, 37:10, (133-143), Online publication date: 1-Oct-2002.
- Hellebrand S, Wunderlich H, Ivaniuk A, Klimets Y and Yarmolik V (2002). Efficient Online and Offline Testing of Embedded DRAMs, IEEE Transactions on Computers, 51:7, (801-809), Online publication date: 1-Jul-2002.
- Forsell M (2002). Architectural differences of efficient sequential and parallel computers, Journal of Systems Architecture: the EUROMICRO Journal, 47:13, (1017-1041), Online publication date: 1-Jul-2002.
- Larus J and Parkes M Using Cohort-Scheduling to Enhance Server Performance Proceedings of the General Track of the annual conference on USENIX Annual Technical Conference, (103-114)
- Papaefstathiou I and Sotiriou C Read, use, simulate, experiment and build Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture, (20-es)
- Pearson M, Armstrong D and McGregor T Using custom hardware and simulation to support computer systems teaching Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture, (5-es)
- Theodoropoulos G (2002). Distributed Simulation of Asynchronous Hardware, Journal of Parallel and Distributed Computing, 62:4, (622-655), Online publication date: 1-Apr-2002.
- Grun P, Dutt N and Nicolau A Memory System Connectivity Exploration Proceedings of the conference on Design, automation and test in Europe
- Mishra P, Dutt N, Nicolau A and Tomiyama H Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units Proceedings of the conference on Design, automation and test in Europe
- Vasiga T (2002). What comes after CS 1 + 2, ACM SIGCSE Bulletin, 34:1, (28-32), Online publication date: 1-Mar-2002.
- Rosti E, Serazzi G, Smirni E and Squillante M (2002). Models of Parallel Applications with Large Computation and I/O Requirements, IEEE Transactions on Software Engineering, 28:3, (286-307), Online publication date: 1-Mar-2002.
- Vasiga T What comes after CS 1 + 2 Proceedings of the 33rd SIGCSE technical symposium on Computer science education, (28-32)
- Rubin S, Bodík R and Chilimbi T An efficient profile-analysis framework for data-layout optimizations Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, (140-153)
- Mishra P, Halambi A, Grun P, Dutt N, Nicolau A and Tomiyama H Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language Proceedings of the 2002 Asia and South Pacific Design Automation Conference
- Gopalan P, Karloff H, Mehta A, Mihail M and Vishnoi N Caching with expiration times Proceedings of the thirteenth annual ACM-SIAM symposium on Discrete algorithms, (540-547)
- Coffman K and Odlyzko A Internet growth Handbook of massive data sets, (47-93)
- Purcell T Parallel ray tracing on a chip Practical parallel rendering, (329-336)
- Rubin S, Bodík R and Chilimbi T (2002). An efficient profile-analysis framework for data-layout optimizations, ACM SIGPLAN Notices, 37:1, (140-153), Online publication date: 1-Jan-2002.
- Lepak K, Bell G and Lipasti M (2001). Silent Stores and Store Value Locality, IEEE Transactions on Computers, 50:11, (1174-1190), Online publication date: 1-Nov-2001.
- Mishra P, Dutt N and Nicolau A Functional abstraction driven design space exploration of heterogeneous programmable architectures Proceedings of the 14th international symposium on Systems synthesis, (256-261)
- Miranda M, Ghez C, Kulkarni C, Catthoor F and Verkest D Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications Proceedings of the 14th international symposium on Systems synthesis, (107-112)
- Lee J and Padua D (2001). Hiding Relaxed Memory Consistency with a Compiler, IEEE Transactions on Computers, 50:8, (824-833), Online publication date: 1-Aug-2001.
- Bobda C and Steenbock N Singular Value Decomposition on Distributed Reconfigurable Systems Proceedings of the 12th International Workshop on Rapid System Prototyping
- Wang W, Raghunathan A, Lakshminarayana G and Jha N Input space adaptive design Proceedings of the 38th annual Design Automation Conference, (738-743)
- Tran N and Reed D ARIMA time series modeling and forecasting for adaptive I/O prefetching Proceedings of the 15th international conference on Supercomputing, (473-485)
- Vuillemin J, Bertin P, Roncin D, Shand M, Touati H and Boucard P Programmable active memories Readings in hardware/software co-design, (611-624)
- Gupta R, Coelho C and De Micheli G Synthesis and simulation of digital systems containing interacting hardware and software components Readings in hardware/software co-design, (544-549)
- Goossens G, Van Praet J, Lanneer D, Geurts W, Kifli A, Liem C and Paulin P Embedded software in real-time signal processing systems Readings in hardware/software co-design, (433-451)
- Gupta R and De Micheli G Hardware-software cosynthesis for digital systems Readings in hardware/software co-design, (5-17)
- Wu L, Weaver C and Austin T CryptoManiac Proceedings of the 28th annual international symposium on Computer architecture, (110-119)
- Wu L, Weaver C and Austin T (2001). CryptoManiac, ACM SIGARCH Computer Architecture News, 29:2, (110-119), Online publication date: 1-May-2001.
- Ng W and Chen P (2001). The Design and Verification of the Rio File Cache, IEEE Transactions on Computers, 50:4, (322-337), Online publication date: 1-Apr-2001.
- Arnold M, Hsiao M, Kremer U and Ryder B (2001). Exploring the Interaction between Java's Implicitly Thrown Exceptions and Instruction Scheduling, International Journal of Parallel Programming, 29:2, (111-137), Online publication date: 1-Apr-2001.
- ELITE Design Methodology of Foundation IP for Improving Synthesis Quality Proceedings of the 2nd International Symposium on Quality Electronic Design
- Wilkes M (2001). The memory gap and the future of high performance memories, ACM SIGARCH Computer Architecture News, 29:1, (2-7), Online publication date: 1-Mar-2001.
- Shackleford B, Snider G, Carter R, Okushi E, Yasuda M, Seo K and Yasuura H (2001). A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine, Genetic Programming and Evolvable Machines, 2:1, (33-60), Online publication date: 1-Mar-2001.
- Johnson E, Ha J and Zaidi M (2001). Lossless Trace Compression, IEEE Transactions on Computers, 50:2, (158-173), Online publication date: 1-Feb-2001.
- Miyaoka Y, Kataoka Y, Togawa N, Yanagisawa M and Ohtsuki T Area/delay estimation for digital signal processor cores Proceedings of the 2001 Asia and South Pacific Design Automation Conference, (156-161)
- Hwang S and Lai F Two cache lines prediction for a wide-issue micro-architecture Proceedings of the 6th Australasian conference on Computer systems architecture, (71-79)
- Hwang S and Lai F (2001). Two cache lines prediction for a wide-issue micro-architecture, Australian Computer Science Communications, 23:4, (71-79), Online publication date: 15-Jan-2001.
- Shackleford B, Okushi E, Yasuda M, Koizumi H, Seo K, Iwamoto T and Yasuura H High-performance hardware design and implementation of genetic algorithms Hardware implementation of intelligent systems, (53-87)
- Hsu P and Liu K (2001). Software optimization of video codecs on pentium processor with MMX technology, EURASIP Journal on Advances in Signal Processing, 2001:1, (100-109), Online publication date: 1-Jan-2001.
- Ghosh S (2001). P2EDAS, IEEE Transactions on Computers, 50:1, (28-50), Online publication date: 1-Jan-2001.
- Pereira P, Heutte L and Lecourtier Y (2001). Source-to-Source Instrumentation for the Optimization of an Automatic Reading System, The Journal of Supercomputing, 18:1, (89-104), Online publication date: 1-Jan-2001.
- Burke J, McDonald J and Austin T (2000). Architectural support for fast symmetric-key cryptography, ACM SIGOPS Operating Systems Review, 34:5, (178-189), Online publication date: 1-Dec-2000.
- Burke J, McDonald J and Austin T (2000). Architectural support for fast symmetric-key cryptography, ACM SIGARCH Computer Architecture News, 28:5, (178-189), Online publication date: 1-Dec-2000.
- Burke J, McDonald J and Austin T Architectural support for fast symmetric-key cryptography Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, (178-189)
- Ziviani N, de Moura E, Navarro G and Baeza-Yates R (2000). Compression, Computer, 33:11, (37-44), Online publication date: 1-Nov-2000.
- Karri R, Kim K and Potkonjak M (2000). Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors, IEEE Transactions on Computers, 49:11, (1272-1284), Online publication date: 1-Nov-2000.
- Campenhout D, Mudge T and Hayes J (2000). Collection and Analysis of Microprocessor Design Errors, IEEE Design & Test, 17:4, (51-60), Online publication date: 1-Oct-2000.
- Leupers R Code generation for embedded processors Proceedings of the 13th international symposium on System synthesis, (173-178)
- Gao G and Sarkar V (2000). Location Consistency-A New Memory Model and Cache Consistency Protocol, IEEE Transactions on Computers, 49:8, (798-813), Online publication date: 1-Aug-2000.
- Kandemir M, Choudhary A, Ramanujam J and Kandaswamy M (2000). A Unified Framework for Optimizing Locality, Parallelism, and Communication in Out-of-Core Computations, IEEE Transactions on Parallel and Distributed Systems, 11:7, (648-668), Online publication date: 1-Jul-2000.
- Cheng F, Unger S and Theobald M (2000). Self-Timed Carry-Lookahead Adders, IEEE Transactions on Computers, 49:7, (659-672), Online publication date: 1-Jul-2000.
- Lepak K and Lipasti M On the value locality of store instructions Proceedings of the 27th annual international symposium on Computer architecture, (182-191)
- Grun P, Dutt N and Nicolau A Memory aware compilation through accurate timing extraction Proceedings of the 37th Annual Design Automation Conference, (316-321)
- Park C, Chung J, Seong B, Roh Y and Park D Boosting superpage utilization with the shadow memory and the partial-subblock TLB Proceedings of the 14th international conference on Supercomputing, (187-195)
- Lepak K and Lipasti M (2000). On the value locality of store instructions, ACM SIGARCH Computer Architecture News, 28:2, (182-191), Online publication date: 1-May-2000.
- Webb B and Louri A (2000). A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems, IEEE Transactions on Parallel and Distributed Systems, 11:5, (444-458), Online publication date: 1-May-2000.
- Ibbett R (2000). HASE DLX Simulation Model, IEEE Micro, 20:3, (57-65), Online publication date: 1-May-2000.
- Blieberger J, Fahringer T and Scholz B (2000). Symbolic Cache Analysis for Real-Time Systems, Real-Time Systems, 18:2/3, (181-215), Online publication date: 1-May-2000.
- Hu Y, Jin G, Johnsson S, Kehagias D and Shalaby N (2000). HPFBench, ACM Transactions on Mathematical Software, 26:1, (99-149), Online publication date: 1-Mar-2000.
- Suh J, Dao B, Duato J and Yalamanchili S (2000). Software-Based Rerouting for Fault-Tolerant Pipelined Communication, IEEE Transactions on Parallel and Distributed Systems, 11:3, (193-211), Online publication date: 1-Mar-2000.
- Gonzalez R (2000). Xtensa, IEEE Micro, 20:2, (60-70), Online publication date: 1-Mar-2000.
- Kumar S, Pires L, Ponnuswamy S, Nanavati C, Golusky J, Vojta M, Wadi S, Pandalai D and Spaanenberg H A benchmark suite for evaluating configurable computing systems—status, reflections, and future directions Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, (126-134)
- Mignotte A, Muller J and Peyran O (2000). Synthesis for Mixed Arithmetic, Design Automation for Embedded Systems, 5:1, (29-60), Online publication date: 1-Feb-2000.
- Grosz B and Gordon P (1999). Conceptions of limited attention and discourse focus, Computational Linguistics, 25:4, (617-624), Online publication date: 1-Dec-1999.
- Wolfe A and Noonburg D A superscalar 3D graphics engine Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, (50-61)
- Khouri K, Lakshminarayana G and Jha N Memory binding for performance optimization of control-flow intensive behaviors Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, (482-488)
- Kandemir M, Banerjee P, Choudhary A, Ramanujam J and Shenoy N (1999). A global communication optimization technique based on data-flow analysis and linear algebra, ACM Transactions on Programming Languages and Systems, 21:6, (1251-1297), Online publication date: 1-Nov-1999.
- Lee C, Potkonjak M and Wolf W (1999). Synthesis of Hard Real-Time Application Specific Systems, Design Automation for Embedded Systems, 4:4, (215-242), Online publication date: 1-Oct-1999.
- Keckler S, Chang A, Lee W, Chatterjee S and Dally W (1999). Concurrent Event Handling through Multithreading, IEEE Transactions on Computers, 48:9, (903-916), Online publication date: 1-Sep-1999.
- Basin D and Friedrich S (1999). Modeling a Hardware Synthesis Methodology in Isabelle, Formal Methods in System Design, 15:2, (99-122), Online publication date: 1-Sep-1999.
- Kandemir M, Banerjee P, Choudhary A, Ramanujam J and Ayguadé E An integer linear programming approach for optimizing cache locality Proceedings of the 13th international conference on Supercomputing, (500-509)
- Karamcheti V, Li C, Pechtchanski I and Yap C A core library for robust numeric and geometric computation Proceedings of the fifteenth annual symposium on Computational geometry, (351-359)
- Van Campenhout D, Mudge T and Hayes J High-level test generation for design verification of pipelined microprocessors Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (185-188)
- Lakshminarayana G, Raghunathan A, Khouri K, Jha N and Dey S Common-case computation Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (56-61)
- Mendelson A and Bekerman M (1999). Design Alternatives of Multithreaded Architecture, International Journal of Parallel Programming, 27:3, (161-193), Online publication date: 1-Jun-1999.
- Yoaz A, Erez M, Ronen R and Jourdan S Speculation techniques for improving load related instruction scheduling Proceedings of the 26th annual international symposium on Computer architecture, (42-53)
- Yoaz A, Erez M, Ronen R and Jourdan S (1999). Speculation techniques for improving load related instruction scheduling, ACM SIGARCH Computer Architecture News, 27:2, (42-53), Online publication date: 1-May-1999.
- Hellebrand S, Wunderlich H, Ivaniuk A, Klimets Y and Yarmolik V Error Detecting Refreshment for Embedded DRAMs Proceedings of the 1999 17TH IEEE VLSI Test Symposium
- Clifton M Logical conditional instructions Proceedings of the 37th annual ACM Southeast Conference (CD-ROM), (24-es)
- del Corral A and Llaberia J (1999). Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems, IEEE Transactions on Computers, 48:4, (449-456), Online publication date: 1-Apr-1999.
- Henry D, Kuszmaul B and Viswanath V The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
- Cardoso J and Vestístias M (1999). Architectures and compilers to support reconfigurable computing, XRDS: Crossroads, The ACM Magazine for Students, 5:3, (15-22), Online publication date: 1-Mar-1999.
- Golla P and Lin E A dynamic scheduling logic for exploiting multiple functional units in single chip multithreaded architectures Proceedings of the 1999 ACM symposium on Applied computing, (466-473)
- Ford B, Hibler M, Lepreau J, McGrath R and Tullmann P Interface and execution models in the Fluke kernel Proceedings of the third symposium on Operating systems design and implementation, (101-115)
- Mocanu O and Oliver J (1999). Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors, Journal of Electronic Testing: Theory and Applications, 14:1-2, (169-180), Online publication date: 1-Feb-1999.
- Ratha N and Jain A (1999). Computer Vision Algorithms on Reconfigurable Logic Arrays, IEEE Transactions on Parallel and Distributed Systems, 10:1, (29-43), Online publication date: 1-Jan-1999.
- Hassoun S Fine grain incremental rescheduling via architectural retiming Proceedings of the 11th international symposium on System synthesis, (158-163)
- Bumble M and Coraor L Architecture for a non-deterministic simulation machine Proceedings of the 30th conference on Winter simulation, (1599-1606)
- Citron D, Feitelson D and Rudolph L (1998). Accelerating multi-media processing by implementing memoing in multiplication and division units, ACM SIGOPS Operating Systems Review, 32:5, (252-261), Online publication date: 1-Dec-1998.
- Cooper K and Harvey T (1998). Compiler-controlled memory, ACM SIGOPS Operating Systems Review, 32:5, (2-11), Online publication date: 1-Dec-1998.
- Citron D, Feitelson D and Rudolph L (1998). Accelerating multi-media processing by implementing memoing in multiplication and division units, ACM SIGPLAN Notices, 33:11, (252-261), Online publication date: 1-Nov-1998.
- Cooper K and Harvey T (1998). Compiler-controlled memory, ACM SIGPLAN Notices, 33:11, (2-11), Online publication date: 1-Nov-1998.
- Hassoun S and Ebeling C Using precomputation in architecture and logic resynthesis Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (316-323)
- Citron D, Feitelson D and Rudolph L Accelerating multi-media processing by implementing memoing in multiplication and division units Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, (252-261)
- Cooper K and Harvey T Compiler-controlled memory Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, (2-11)
- Lappalainen V Performance analysis of Intel MMX technology for an H.263 video H.263 video encoder Proceedings of the sixth ACM international conference on Multimedia, (309-314)
- Golla P and Lin E (1998). A comparison of the effect of branch prediction on multithreaded and scalar architectures, ACM SIGARCH Computer Architecture News, 26:4, (3-11), Online publication date: 1-Sep-1998.
- Moore J, Lynch T and Kaufmann M (1998). A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program, IEEE Transactions on Computers, 47:9, (913-926), Online publication date: 1-Sep-1998.
- Kuskin J, Ofelt D, Heinrich M, Heinlein J, Simoni R, Gharachorloo K, Chapin J, Nakahira D, Baxter J, Horowitz M, Gupta A, Rosenblum M and Hennessy J The Stanford FLASH multiprocessor 25 years of the international symposia on Computer architecture (selected papers), (485-496)
- Lundberg L and Häggander D Bounding on the gain of optimizing data layout in vector processors Proceedings of the 12th international conference on Supercomputing, (235-242)
- González J and González A The potential of data value speculation to boost ILP Proceedings of the 12th international conference on Supercomputing, (21-28)
- Soundararajan V, Heinrich M, Verghese B, Gharachorloo K, Gupta A and Hennessy J (1998). Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors, ACM SIGARCH Computer Architecture News, 26:3, (342-355), Online publication date: 1-Jun-1998.
- Cox M, Bhandari N and Shantz M (1998). Multi-level texture caching for 3D graphics hardware, ACM SIGARCH Computer Architecture News, 26:3, (86-97), Online publication date: 1-Jun-1998.
- Van Campenhout J, Verplaetse P and Neefs H ESCAPE Proceedings of the 1998 workshop on Computer architecture education, (9-es)
- Koh S (1998). VHDL Modeling of Optoelectronic Interconnect Networks, Analog Integrated Circuits and Signal Processing, 16:2, (111-119), Online publication date: 1-Jun-1998.
- Lee C, Kin J, Potkonjak M and Mangione-Smith W Media architecture Proceedings of the 35th annual Design Automation Conference, (321-326)
- Soundararajan V, Heinrich M, Verghese B, Gharachorloo K, Gupta A and Hennessy J Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors Proceedings of the 25th annual international symposium on Computer architecture, (342-355)
- Cox M, Bhandari N and Shantz M Multi-level texture caching for 3D graphics hardware Proceedings of the 25th annual international symposium on Computer architecture, (86-97)
- Bahadur S, Kalyanakrishnan V and Westall J An empirical study of the effects of careful page placement in Linux Proceedings of the 36th annual ACM Southeast Conference, (241-250)
- Cao P and Liu C (1998). Maintaining Strong Cache Consistency in the World Wide Web, IEEE Transactions on Computers, 47:4, (445-457), Online publication date: 1-Apr-1998.
- Vingralek R, Breitbart Y and Weikum G (1998). Snowball, Distributed and Parallel Databases, 6:2, (117-156), Online publication date: 1-Apr-1998.
- Woods R, Trainor D and Heron J (1998). Applying an XC6200 to Real-Time Image Processing, IEEE Design & Test, 15:1, (30-38), Online publication date: 1-Jan-1998.
- Linderman R, Kohler R and Linderman M (1998). A Dependable High Performance Wafer Scale Architecture for Embedded Signal Processing, IEEE Transactions on Computers, 47:1, (125-128), Online publication date: 1-Jan-1998.
- Bennett J and Flynn M Prediction caches for superscalar processors Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, (81-90)
- Karp A and Markstein P (1997). High-precision division and square root, ACM Transactions on Mathematical Software, 23:4, (561-589), Online publication date: 1-Dec-1997.
- Vajracharya S and Grunwald D Loop re-ordering and pre-fetching at run-time Proceedings of the 1997 ACM/IEEE conference on Supercomputing, (1-13)
- Tupuri R and Abraham J A Novel Functional Test Generation Method for Processors using Commercial ATPG Proceedings of the 1997 IEEE International Test Conference
- Fink S, Baden S, Huston C and Jansen K (1997). Parallel Cluster Identification for Multidimensional Lattices, IEEE Transactions on Parallel and Distributed Systems, 8:11, (1089-1097), Online publication date: 1-Nov-1997.
- Werner T and Akella V (1997). Asynchronous Processor Survey, Computer, 30:11, (67-76), Online publication date: 1-Nov-1997.
- Phalke V and Gopinath B (1997). Compression-Based Program Characterization for Improving Cache Memory Performance, IEEE Transactions on Computers, 46:11, (1174-1186), Online publication date: 1-Nov-1997.
- Shi W, Hu W and Tang Z (1997). An interaction of coherence protocols and memory consistency models in DSM systems, ACM SIGOPS Operating Systems Review, 31:4, (41-54), Online publication date: 1-Oct-1997.
- Jacobson H and Gopalakrishnan G Asynchronous Microengines for Efficient High-level Control Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
- Krishnaswamy V, Hasteer G and Banerjee P Load Balancing and Workload Minimization Of Overlapping Parallel Tasks Proceedings of the international Conference on Parallel Processing, (272-279)
- Dai D and Panda D How Much Does Network Contention Affect Distributed Shared Memory Performance? Proceedings of the international Conference on Parallel Processing
- Athas W, Tzartzanis N, Svensson L, Peterson L, Li H, Jiang X, Wang P and Liu W AC-1 Proceedings of the 1997 international symposium on Low power electronics and design, (328-333)
- Draves S (1997). Implementing bit-addressing with specialization, ACM SIGPLAN Notices, 32:8, (239-250), Online publication date: 1-Aug-1997.
- Draves S Implementing bit-addressing with specialization Proceedings of the second ACM SIGPLAN international conference on Functional programming, (239-250)
- Dogimont S, Gumm M, Mombers F, Mlynek D and Torielli A Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
- González A, Valero M, Topham N and Parcerisa J Eliminating cache conflict misses through XOR-based placement functions Proceedings of the 11th international conference on Supercomputing, (76-83)
- Doettling G, Getzlaff K, Leppla B, Lipponer W, Pflueger T, Schlipf T, Schmunkamp D and Wille U (1997). S/390 parallel enterprise server generation 3, IBM Journal of Research and Development, 41:4-5, (405-428), Online publication date: 1-Jul-1997.
- Mahapatra N and Dutt S (1997). Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search, IEEE Transactions on Parallel and Distributed Systems, 8:7, (738-756), Online publication date: 1-Jul-1997.
- Shastri V, Rangan P and Sampath-Kumar S (1997). DVDs, Multimedia Tools and Applications, 5:1, (33-63), Online publication date: 1-Jul-1997.
- Lee M, Min S, Shin H, Kim C and Park C (1997). Threaded Prefetching, Real-Time Systems, 13:1, (47-65), Online publication date: 1-Jul-1997.
- Gupta A, Malik S and Ashar P Toward formalizing a validation methodology using simulation coverage Proceedings of the 34th annual Design Automation Conference, (740-745)
- Gibbons P, Matias Y and Ramachandran V Can shared-memory model serve as a bridging model for parallel computation? Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures, (72-83)
- Jiménez-Pérez G and Batory D (1997). Memory simulators and software generators, ACM SIGSOFT Software Engineering Notes, 22:3, (136-145), Online publication date: 1-May-1997.
- Jiménez-Pérez G and Batory D Memory simulators and software generators Proceedings of the 1997 symposium on Software reusability, (136-145)
- Park K and Park K Events suppression technique for high performance VHDL simulation Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
- Hu Y, Johnsson S, Kehagias D and Shalaby N DPF Proceedings of the 11th International Symposium on Parallel Processing, (219-226)
- Abu-Ghazaleh N, Wilsey P, Fan X and Hensgen D (1997). Synthesizing Variable Instruction Issue Interpreters for Implementing Functional Parallelism on SIMD Computers, IEEE Transactions on Parallel and Distributed Systems, 8:4, (412-423), Online publication date: 1-Apr-1997.
- Gunther B (1997). Multithreading with Distributed Functional Units, IEEE Transactions on Computers, 46:4, (399-411), Online publication date: 1-Apr-1997.
- Walker P and Ghosh S Exploiting temporal independence in distributed preemptive circuit simulation Proceedings of the 1997 European conference on Design and Test
- Shoji M, Hirose F, Shimogori S, Kowatari S and Nagai H Acceleration of Behavioral Simulation on Simulation Specific Machines Proceedings of the 1997 European conference on Design and Test
- Claypool M and Riedl J A quality planning model for distributed multimedia in the virtual cockpit Proceedings of the fourth ACM international conference on Multimedia, (253-264)
- Finkler U and Mehlhorn K Runtime prediction of real programs on real machines Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms, (380-389)
- LaMarca A and Ladner R The influence of caches on the performance of sorting Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms, (370-379)
- Fiat A and Rosen Z Experimental studies of access graph based heuristics Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms, (63-72)
- Cheng F, Unger S, Theobald M and Cho W Delay-Insensitive Carry-Lookahead Adders Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
- Hong I and Potkonjak M Power optimization in disk-based real-time application specific systems Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, (634-637)
- Kim K, Karri R and Potkonjak M Heterogeneous built-in resiliency of application specific programmable processors Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, (406-411)
- Wilberg J and Camposano R (1997). VLIW Processor Codesign for Video Processing, Design Automation for Embedded Systems, 2:1, (79-119), Online publication date: 1-Jan-1997.
- Romer T, Lee D, Voelker G, Wolman A, Wong W, Baer J, Bershad B and Levy H (1996). The structure and performance of interpreters, ACM SIGOPS Operating Systems Review, 30:5, (150-159), Online publication date: 1-Dec-1996.
- Huang A and Shen J (1996). The intrinsic bandwidth requirements of ordinary programs, ACM SIGOPS Operating Systems Review, 30:5, (105-114), Online publication date: 1-Dec-1996.
- Chen P, Ng W, Chandra S, Aycock C, Rajamani G and Lowell D (1996). The Rio file cache, ACM SIGOPS Operating Systems Review, 30:5, (74-83), Online publication date: 1-Dec-1996.
- del Corral A and Llaberia J Increasing the effective bandwidth of complex memory systems in multivector processors Proceedings of the 1996 ACM/IEEE conference on Supercomputing, (26-es)
- Docy S, Hong I and Potkonjak M Throughput Optimization in Disk-Based Real-Time Application Specific Systems Proceedings of the 9th international symposium on System synthesis
- Zivojnovic V, Pees S, Schlager C, Willems M, Schoenen R and Meyr H DSP processor/compiler co-design Proceedings of the 9th international symposium on System synthesis
- Dabbous W, O'Malley S and Castelluccia C (1996). Generating efficient protocol code from an abstract specification, ACM SIGCOMM Computer Communication Review, 26:4, (60-72), Online publication date: 1-Oct-1996.
- Romer T, Lee D, Voelker G, Wolman A, Wong W, Baer J, Bershad B and Levy H The structure and performance of interpreters Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, (150-159)
- Huang A and Shen J The intrinsic bandwidth requirements of ordinary programs Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, (105-114)
- Chen P, Ng W, Chandra S, Aycock C, Rajamani G and Lowell D The Rio file cache Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, (74-83)
- Chen C and Somani A (1996). Architecture Technique Trade-Offs Using Mean Memory Delay Time, IEEE Transactions on Computers, 45:10, (1089-1100), Online publication date: 1-Oct-1996.
- Gschwind M and Maurer D An extendable MIPS-I processor kernel in VHDL for hardware/software co-design Proceedings of the conference on European design automation, (548-553)
- Romer T, Lee D, Voelker G, Wolman A, Wong W, Baer J, Bershad B and Levy H (1996). The structure and performance of interpreters, ACM SIGPLAN Notices, 31:9, (150-159), Online publication date: 1-Sep-1996.
- Huang A and Shen J (1996). The intrinsic bandwidth requirements of ordinary programs, ACM SIGPLAN Notices, 31:9, (105-114), Online publication date: 1-Sep-1996.
- Chen P, Ng W, Chandra S, Aycock C, Rajamani G and Lowell D (1996). The Rio file cache, ACM SIGPLAN Notices, 31:9, (74-83), Online publication date: 1-Sep-1996.
- Páez-Monzón G and Páez-Monzón C (1996). The RISC processor DMN-6: a unified data-control flow architecture, ACM SIGARCH Computer Architecture News, 24:4, (3-10), Online publication date: 1-Sep-1996.
- Lacroute P (1996). Analysis of a Parallel Volume Rendering System Based on the Shear-Warp Factorization, IEEE Transactions on Visualization and Computer Graphics, 2:3, (218-231), Online publication date: 1-Sep-1996.
- Dabbous W, O'Malley S and Castelluccia C Generating efficient protocol code from an abstract specification Conference proceedings on Applications, technologies, architectures, and protocols for computer communications, (60-72)
- Allen J and Schimmel D (1996). Issues in the Design of High Performance SIMD Architectures, IEEE Transactions on Parallel and Distributed Systems, 7:8, (818-829), Online publication date: 1-Aug-1996.
- Giladi R (1996). Evaluating the Mflops Measure, IEEE Micro, 16:4, (69-75), Online publication date: 1-Aug-1996.
- Peleg A and Weiser U (1996). MMX Technology Extension to the Intel Architecture, IEEE Micro, 16:4, (42-50), Online publication date: 1-Aug-1996.
- Lee C and Parng T (1996). A Subsystem-Oriented Performance Analysis Methodology for Shared-Bus Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, 7:7, (755-767), Online publication date: 1-Jul-1996.
- Bui T and Moon B (1996). Genetic Algorithm and Graph Partitioning, IEEE Transactions on Computers, 45:7, (841-855), Online publication date: 1-Jul-1996.
- Carro L, Pereira and Suzim A Prototyping and reengineering of microcontroller-based systems Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
- Coe P, Williams L and Ibbett R (1996). An interactive environment for the teaching of computer architecture, ACM SIGCSE Bulletin, 28:SI, (33-35), Online publication date: 2-Jun-1996.
- Coe P, Williams L and Ibbett R An interactive environment for the teaching of computer architecture Proceedings of the 1st conference on Integrating technology into computer science education, (33-35)
- Bryant R Bit-level analysis of an SRT divider circuit Proceedings of the 33rd annual Design Automation Conference, (661-665)
- Sanghavi J, Ranjan R, Brayton R and Sangiovanni-Vincentelli A High performance BDD package by exploiting memory hierarchy Proceedings of the 33rd annual Design Automation Conference, (635-640)
- Gupta R Analysis of operation delay and execution rate constraints for embedded systems Proceedings of the 33rd annual Design Automation Conference, (601-604)
- Burch J Techniques for verifying superscalar microprocessors Proceedings of the 33rd annual Design Automation Conference, (552-557)
- Hosseini A, Mavroidis D and Konas P Code generation and analysis for the functional verification of micro processors Proceedings of the 33rd annual Design Automation Conference, (305-310)
- Toledo S and Gustavson F The design and implementation of SOLAR, a portable library for scalable out-of-core linear algebra computations Proceedings of the fourth workshop on I/O in parallel and distributed systems: part of the federated computing research conference, (28-40)
- Martonosi M, Ofelt D and Heinrich M Integrating performance monitoring and communication in parallel computers Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, (138-147)
- Harchol-Balter M and Downey A Exploiting process lifetime distributions for dynamic load balancing Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, (13-24)
- Martonosi M, Ofelt D and Heinrich M (1996). Integrating performance monitoring and communication in parallel computers, ACM SIGMETRICS Performance Evaluation Review, 24:1, (138-147), Online publication date: 15-May-1996.
- Harchol-Balter M and Downey A (1996). Exploiting process lifetime distributions for dynamic load balancing, ACM SIGMETRICS Performance Evaluation Review, 24:1, (13-24), Online publication date: 15-May-1996.
- Austin T and Sohi G High-bandwidth address translation for multiple-issue processors Proceedings of the 23rd annual international symposium on Computer architecture, (158-167)
- Wilson K, Olukotun K and Rosenblum M Increasing cache port efficiency for dynamic superscalar microprocessors Proceedings of the 23rd annual international symposium on Computer architecture, (147-157)
- Austin T and Sohi G (1996). High-bandwidth address translation for multiple-issue processors, ACM SIGARCH Computer Architecture News, 24:2, (158-167), Online publication date: 1-May-1996.
- Wilson K, Olukotun K and Rosenblum M (1996). Increasing cache port efficiency for dynamic superscalar microprocessors, ACM SIGARCH Computer Architecture News, 24:2, (147-157), Online publication date: 1-May-1996.
- Blumofe R, Frigo M, Joerg C, Leiserson C and Randall K Dag-Consistent Distributed Shared Memory Proceedings of the 10th International Parallel Processing Symposium, (132-141)
- Williams L Simulating the DASH Architecture in HASE Proceedings of the 29th Annual Simulation Symposium (SS '96)
- Chen T Efficient trace-sampling simulation techniques for cache performance analysis Proceedings of the 29th Annual Simulation Symposium (SS '96)
- Tyson G and Farrens M (1996). Evaluating the Effects of Predicated Execution on Branch Prediction, International Journal of Parallel Programming, 24:2, (159-186), Online publication date: 1-Apr-1996.
- Zheng L and Larson P (1996). Speeding Up External Mergesort, IEEE Transactions on Knowledge and Data Engineering, 8:2, (322-332), Online publication date: 1-Apr-1996.
- Dutt S and Assaad F (1996). Mantissa-Preserving Operations and Robust Algorithm-Based Fault Tolerance for Matrix Computations, IEEE Transactions on Computers, 45:4, (408-424), Online publication date: 1-Apr-1996.
- Hardt W and Rosenstiel W Speed-up estimation for HW/SW-systems Proceedings of the 4th International Workshop on Hardware/Software Co-Design
- Garside J, Temple S and Mehra R The AMULET2e Cache System Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
- Tomiyama H and Yasuura H Optimal Code Placement of Embedded Software for Instruction Caches Proceedings of the 1996 European conference on Design and Test
- Ikeda M, Okubo T, Abe T, Ito Y, Tashiro Y and Kasai R A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set Proceedings of the 1996 European conference on Design and Test
- Inamori M, Naganuma J, Wakabayashi H and Endo M A Memory-based Architecture for MPEG2 System Protocol LSIs Proceedings of the 1996 European conference on Design and Test
- Yu Hu and Johnsson S (1996). A Data-Parallel Implementation of Hierarchical N-Body Methods, International Journal of High Performance Computing Applications, 10:1, (3-40), Online publication date: 1-Mar-1996.
- Merchant A and Yu P (1996). Analytic Modeling of Clustered RAID with Mapping Based on Nearly Random Permutation, IEEE Transactions on Computers, 45:3, (367-373), Online publication date: 1-Mar-1996.
- Chang M and Lai F (1996). Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme, IEEE Transactions on Computers, 45:3, (278-293), Online publication date: 1-Mar-1996.
- Goudge L and Segars S Thumb Proceedings of the 41st IEEE International Computer Conference
- Kuhn B and Binkley D An enabling optimization for C++ virtual functions Proceedings of the 1996 ACM symposium on Applied Computing, (420-428)
- Iyengar V, Trevillyan L and Bose P Representative Traces for Processor Models with Infinite Cache Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
- Nayfeh B, Olukotun K and Singh J The impact of shared-cache clustering in small-scale shared-memory multiprocessors Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
- Blumrich M, Dubnicki C, Felten E and Li K Protected, user-level DMA for the SHRIMP network interface Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
- Rajamony R and Cox A A Performance Debugger for Eliminating Excess Synchronization in Shared-Memory Parallel Programs Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
- Xu Z Simulation of Heterogeneous Networks of Workstations Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
- Markatos E Using Remote Memory to avoid Disk Thrashing Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
- Burgess B (1996). What RISC penalty?, IEEE Micro, 16:1, (80), Online publication date: 1-Feb-1996.
- Murphy B, Zeadally S and Adams C An analysis of process and memory models to support high-speed networking in a UNIX environment Proceedings of the 1996 annual conference on USENIX Annual Technical Conference, (20-20)
- Markatos E and Dramitinos G Implementation of a reliable remote memory pager Proceedings of the 1996 annual conference on USENIX Annual Technical Conference, (15-15)
- Farcy A and Temam O Improving single-process performance with multithreaded processors Proceedings of the 10th international conference on Supercomputing, (350-357)
- LaMarca A and Ladner R (1996). The influence of caches on the performance of heaps, ACM Journal of Experimental Algorithmics, 1, (4-es), Online publication date: 1-Jan-1996.
- Hamblen J, Owen H, Yalamanchili S and Dao B Using rapid prototyping in computer architecture design laboratories Proceedings of the 1996 workshop on Computer architecture education, (4-es)
- Coe P, Williams L and Ibbett R (1996). An interactive environment for the teaching of computer architecture, ACM SIGCUE Outlook, 24:1-3, (33-35), Online publication date: 1-Jan-1996.
- Talluri M, Hill M and Khalidi Y (1995). A new page table for 64-bit address spaces, ACM SIGOPS Operating Systems Review, 29:5, (184-200), Online publication date: 3-Dec-1995.
- Talluri M, Hill M and Khalidi Y A new page table for 64-bit address spaces Proceedings of the fifteenth ACM symposium on Operating systems principles, (184-200)
- Lozano L and Gao G Exploiting short-lived variables in superscalar processors Proceedings of the 28th annual international symposium on Microarchitecture, (292-302)
- Fagin B and Russell K Partial resolution in branch target buffers Proceedings of the 28th annual international symposium on Microarchitecture, (193-198)
- Huang A and Shen J A limit study of local memory requirements using value reuse profiles Proceedings of the 28th annual international symposium on Microarchitecture, (71-81)
- Ahuja P, Clark D and Rogers A The performance impact of incomplete bypassing in processor pipelines Proceedings of the 28th annual international symposium on Microarchitecture, (36-45)
- Jones R, Dill D and Burch J Efficient validity checking for processor verification Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, (2-6)
- Awaga M, Ohtsuka T, Yoshizawa H and Sasaki S (1995). 3D Graphics Processor Chip Set, IEEE Micro, 15:6, (37-45), Online publication date: 1-Dec-1995.
- Hasegawa A, Kawasaki I, Yamada K, Yoshioka S, Kawasaki S and Biswas P (1995). SH3, IEEE Micro, 15:6, (11-19), Online publication date: 1-Dec-1995.
- Mital A and Fagin B (1995). The Performance of Counter- and Correlation-Based Schemes for Branch Target Buffers, IEEE Transactions on Computers, 44:12, (1383-1393), Online publication date: 1-Dec-1995.
- Luk C Memory disambiguation for general-purpose applications Proceedings of the 1995 conference of the Centre for Advanced Studies on Collaborative research
- Cook G and Delp E (1995). An Investigation of Scalable SIMD I/O Techniques with Application to Parallel JPEG Compression, Journal of Parallel and Distributed Computing, 30:2, (111-128), Online publication date: 1-Nov-1995.
- Busquets-Mataix J and Serrano-Martin J The impact of extrinsic cache performance on predictability of real-time systems Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications
- Boquist U Interprocedural register allocation for lazy functional languages Proceedings of the seventh international conference on Functional programming languages and computer architecture, (270-281)
- Bekerman M and Mendelson A (1995). A Performance Analysis of Pentium Processor Systems, IEEE Micro, 15:5, (72-83), Online publication date: 1-Oct-1995.
- Segars S, Clarke K and Goudge L (1995). Embedded Control Problems, Thumb, and the ARM7TDMI, IEEE Micro, 15:5, (22-30), Online publication date: 1-Oct-1995.
- Panda P and Dutt N 1995 high level synthesis design repository Proceedings of the 8th international symposium on System synthesis, (170-174)
- Jain R and Werth J (1995). Airdisks and airRAID (expanded extract), ACM SIGARCH Computer Architecture News, 23:4, (23-28), Online publication date: 1-Sep-1995.
- Feitelson D, Corbett P, Johnson Baylor S and Hsu Y (1995). Parallel I/O Subsystems in Massively Parallel Supercomputers, IEEE Parallel & Distributed Technology: Systems & Technology, 3:3, (33-47), Online publication date: 1-Sep-1995.
- Chen S, Alewine N, Kent Fuchs W and Hwu W (1995). Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer, IEEE Transactions on Computers, 44:9, (1096-1107), Online publication date: 1-Sep-1995.
- Anderson J, Amarasinghe S and Lam M (1995). Data and computation transformations for multiprocessors, ACM SIGPLAN Notices, 30:8, (166-178), Online publication date: 1-Aug-1995.
- Anderson J, Amarasinghe S and Lam M Data and computation transformations for multiprocessors Proceedings of the fifth ACM SIGPLAN symposium on Principles and practice of parallel programming, (166-178)
- Giladi R and Ahituv N (1995). SPEC as a Performance Evaluation Measure, Computer, 28:8, (33-42), Online publication date: 1-Aug-1995.
- Stamatopoulos J and Solworth J Universal congestion control for meshes Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures, (165-174)
- Drach N Hardware implementation issues of data prefetching Proceedings of the 9th international conference on Supercomputing, (245-254)
- Li W Compiler cache optimizations for banded matrix problems Proceedings of the 9th international conference on Supercomputing, (21-30)
- Austin T, Pnevmatikatos D and Sohi G Streamlining data cache access with fast address calculation Proceedings of the 22nd annual international symposium on Computer architecture, (369-380)
- Uhlig R, Nagle D, Mudge T, Sechrest S and Emer J Instruction fetching Proceedings of the 22nd annual international symposium on Computer architecture, (345-356)
- Diep T, Nelson C and Shen J Performance evaluation of the PowerPC 620 microarchitecture Proceedings of the 22nd annual international symposium on Computer architecture, (163-174)
- Simone M, Essen A, Ike A, Krishnamoorthy A, Maruyama T, Patkar N, Ramaswami M, Shebanow M, Thirumalaiswamy V and Tovey D Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor Proceedings of the 22nd annual international symposium on Computer architecture, (151-162)
- Figueroa S (1995). When is double rounding innocuous?, ACM SIGNUM Newsletter, 30:3, (21-26), Online publication date: 1-Jul-1995.
- Lim S, Bae Y, Jang G, Rhee B, Min S, Park C, Shin H, Park K, Moon S and Kim C (1995). An Accurate Worst Case Timing Analysis for RISC Processors, IEEE Transactions on Software Engineering, 21:7, (593-604), Online publication date: 1-Jul-1995.
- Inoue K, Shintani Y, Kamada E and Shonai T (1995). A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers, IEEE Transactions on Computers, 44:7, (891-902), Online publication date: 1-Jul-1995.
- Diep T Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
- Turumella B, Kabakibo A, Bogadi M, Menon K, Thusoo S and Chow M Design Verification of a Super-Scalar RISC Processor Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
- Osone H, Thusoo S, Dharmaraj A and Chia B Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
- Drach N, Seznec A and Windheiser D Direct-mapped versus set-associative pipelined caches Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, (79-88)
- Ertl M Stack caching for interpreters Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation, (315-327)
- Cierniak M and Li W Unifying data and control transformations for distributed shared-memory machines Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation, (205-217)
- Mueller F and Whalley D Avoiding conditional branches by code replication Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation, (56-66)
- Ertl M (1995). Stack caching for interpreters, ACM SIGPLAN Notices, 30:6, (315-327), Online publication date: 1-Jun-1995.
- Cierniak M and Li W (1995). Unifying data and control transformations for distributed shared-memory machines, ACM SIGPLAN Notices, 30:6, (205-217), Online publication date: 1-Jun-1995.
- Mueller F and Whalley D (1995). Avoiding conditional branches by code replication, ACM SIGPLAN Notices, 30:6, (56-66), Online publication date: 1-Jun-1995.
- Parhi K and Srinivas H (1995). A Fast Radix-4 Division Algorithm and its Architecture, IEEE Transactions on Computers, 44:6, (826-831), Online publication date: 1-Jun-1995.
- Austin T, Pnevmatikatos D and Sohi G (1995). Streamlining data cache access with fast address calculation, ACM SIGARCH Computer Architecture News, 23:2, (369-380), Online publication date: 1-May-1995.
- Uhlig R, Nagle D, Mudge T, Sechrest S and Emer J (1995). Instruction fetching, ACM SIGARCH Computer Architecture News, 23:2, (345-356), Online publication date: 1-May-1995.
- Diep T, Nelson C and Shen J (1995). Performance evaluation of the PowerPC 620 microarchitecture, ACM SIGARCH Computer Architecture News, 23:2, (163-174), Online publication date: 1-May-1995.
- Simone M, Essen A, Ike A, Krishnamoorthy A, Maruyama T, Patkar N, Ramaswami M, Shebanow M, Thirumalaiswamy V and Tovey D (1995). Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor, ACM SIGARCH Computer Architecture News, 23:2, (151-162), Online publication date: 1-May-1995.
- Phalke V and Gopinath B An inter-reference gap model for temporal locality in program behavior Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, (291-300)
- Phalke V and Gopinath B (1995). An inter-reference gap model for temporal locality in program behavior, ACM SIGMETRICS Performance Evaluation Review, 23:1, (291-300), Online publication date: 1-May-1995.
- Circello J, Edgington G, McCarthy D, Gay J, Schimke D, Sullivan S, Duerden R, Hinds C, Marquette D, Sood L, Crouch A and Chow D (1995). The Superscalar Architecture of the MC68060, IEEE Micro, 15:2, (10-21), Online publication date: 1-Apr-1995.
- Ranade A, Taylor V and Messerschmitt D (1995). SPAR, IEEE Transactions on Computers, 44:4, (531-545), Online publication date: 1-Apr-1995.
- Casavant A Balancing structural hazards and hardware cost of pipelined processors Proceedings of the 1995 European conference on Design and Test
- Fauth A, Van Praet J and Freericks M Describing instruction set processors using nML Proceedings of the 1995 European conference on Design and Test
- Kifli A, Goosens G and De Man H A unified scheduling model for high-level synthesis and code generation Proceedings of the 1995 European conference on Design and Test
- Wulf W and McKee S (1995). Hitting the memory wall, ACM SIGARCH Computer Architecture News, 23:1, (20-24), Online publication date: 1-Mar-1995.
- IEEE Transactions on Computers Staff (1995). Practical Delay Enforced Multistream (DEMUS) Control of Deeply Pipelined Processors, IEEE Transactions on Computers, 44:3, (458-462), Online publication date: 1-Mar-1995.
- Anderson T, Culler D, Patterson D and and the NOW team (1995). A Case for NOW (Networks of Workstations), IEEE Micro, 15:1, (54-64), Online publication date: 1-Feb-1995.
- Saxena N, Chang C, Dawallu K, Kohli J and Helland P (1995). Fault-Tolerant Features in the HaL Memory Management Unit, IEEE Transactions on Computers, 44:2, (170-180), Online publication date: 1-Feb-1995.
- Citron D and Rudolph L Creating a wider bus using caching techniques Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
- Garg V and Schimmel D Architectural support for inter-stream communication in a MSIMD system Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
- Temam O and Drach N Software assistance for data caches Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
- Theobald K, Hum H and Gao G A Design Frame for Hybrid Access Cashes Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
- Frezza S, Levitan S and Chrysanthis P Requirements-based design evaluation Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, (76-81)
- Bose P Use of architectural simulation tools in education Proceedings of the 1995 workshop on Computer architecture education, (7-es)
- Siewiorek D Tradition and change Proceedings of the 1995 workshop on Computer architecture education, (1-es)
- Heinrich M, Kuskin J, Ofelt D, Heinlein J, Baxter J, Singh J, Simoni R, Gharachorloo K, Nakahira D, Horowitz M, Gupta A, Rosenblum M and Hennessy J (1994). The performance impact of flexibility in the Stanford FLASH multiprocessor, ACM SIGOPS Operating Systems Review, 28:5, (274-285), Online publication date: 1-Dec-1994.
- Talluri M and Hill M (1994). Surpassing the TLB performance of superpages with less operating system support, ACM SIGOPS Operating Systems Review, 28:5, (171-182), Online publication date: 1-Dec-1994.
- Maynard A, Donnelly C and Olszewski B (1994). Contrasting characteristics and cache performance of technical and multi-user commercial workloads, ACM SIGOPS Operating Systems Review, 28:5, (145-156), Online publication date: 1-Dec-1994.
- Schmidt W and Nilsen K (1994). Performance of a hardware-assisted real-time garbage collector, ACM SIGOPS Operating Systems Review, 28:5, (76-85), Online publication date: 1-Dec-1994.
- Sosič R (1994). History cache, ACM SIGARCH Computer Architecture News, 22:5, (11-18), Online publication date: 1-Dec-1994.
- Tyson G The effects of predicated execution on branch prediction Proceedings of the 27th annual international symposium on Microarchitecture, (196-206)
- Razdan R and Smith M A high-performance microarchitecture with hardware-programmable functional units Proceedings of the 27th annual international symposium on Microarchitecture, (172-180)
- Franklin M and Smotherman M A fill-unit approach to multiple instruction issue Proceedings of the 27th annual international symposium on Microarchitecture, (162-171)
- Noonburg D and Shen J Theoretical modeling of superscalar processor performance Proceedings of the 27th annual international symposium on Microarchitecture, (52-62)
- Pasquale B and Polyzos G Dynamic I/O characterization of I/O intensive scientific applications Proceedings of the 1994 ACM/IEEE conference on Supercomputing, (660-669)
- Dahlin M, Wang R, Anderson T and Patterson D Cooperative caching Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation, (19-es)
- Bala K, Kaashoek M and Weihl W Software prefetching and caching for translation lookaside buffers Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation, (18-es)
- Iwashita H, Kowatari S, Nakata T and Hirose F Automatic test program generation for pipelined processors Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, (580-583)
- Goossens G, Bolsens I, Lin B and Catthoor F Design of heterogeneous ICs for mobile and personal communication systems Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, (524-531)
- Heinrich M, Kuskin J, Ofelt D, Heinlein J, Baxter J, Singh J, Simoni R, Gharachorloo K, Nakahira D, Horowitz M, Gupta A, Rosenblum M and Hennessy J The performance impact of flexibility in the Stanford FLASH multiprocessor Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, (274-285)
- Talluri M and Hill M Surpassing the TLB performance of superpages with less operating system support Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, (171-182)
- Maynard A, Donnelly C and Olszewski B Contrasting characteristics and cache performance of technical and multi-user commercial workloads Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, (145-156)
- Schmidt W and Nilsen K Performance of a hardware-assisted real-time garbage collector Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, (76-85)
- Heinrich M, Kuskin J, Ofelt D, Heinlein J, Baxter J, Singh J, Simoni R, Gharachorloo K, Nakahira D, Horowitz M, Gupta A, Rosenblum M and Hennessy J (1994). The performance impact of flexibility in the Stanford FLASH multiprocessor, ACM SIGPLAN Notices, 29:11, (274-285), Online publication date: 1-Nov-1994.
- Talluri M and Hill M (1994). Surpassing the TLB performance of superpages with less operating system support, ACM SIGPLAN Notices, 29:11, (171-182), Online publication date: 1-Nov-1994.
- Maynard A, Donnelly C and Olszewski B (1994). Contrasting characteristics and cache performance of technical and multi-user commercial workloads, ACM SIGPLAN Notices, 29:11, (145-156), Online publication date: 1-Nov-1994.
- Schmidt W and Nilsen K (1994). Performance of a hardware-assisted real-time garbage collector, ACM SIGPLAN Notices, 29:11, (76-85), Online publication date: 1-Nov-1994.
- Silva C and Kaufman A Parallel performance measures for volume ray casting Proceedings of the conference on Visualization '94, (196-203)
- Janssens B and Fuchs W (1994). The Performance of Cache-Based Error Recovery in Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, 5:10, (1033-1043), Online publication date: 1-Oct-1994.
- Kumar R and Tahar S Formal verification of pipeline conflicts in RISC processors Proceedings of the conference on European design automation, (284-289)
- Wilberg J, Camposano R and Rosenstiel W Design flow for hardware/software cosynthesis of a video compression system Proceedings of the 3rd international workshop on Hardware/software co-design, (73-80)
- Gupta R and De Micheli G Constrained software generation for hardware-software systems Proceedings of the 3rd international workshop on Hardware/software co-design, (56-63)
- Vaden M, Merkel L, Moore C, Potter T and Reese R (1994). Design considerations for the PowerPC 601 microprocessor, IBM Journal of Research and Development, 38:5, (605-620), Online publication date: 1-Sep-1994.
- Wu P and Wang F (1994). Padded string, ACM SIGPLAN Notices, 29:9, (64-67), Online publication date: 1-Sep-1994.
- Fagin B and Renard C (1994). Field programmable gate arrays and floating point arithmetic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2:3, (365-367), Online publication date: 1-Sep-1994.
- Yang Q and Adina S A One's Complement Cache Memory Proceedings of the 1994 International Conference on Parallel Processing - Volume 01, (250-257)
- SUMITA E, NISIYAMA N and IIDA H The relationship between architectures and example-retrieval times Proceedings of the Twelfth AAAI National Conference on Artificial Intelligence, (478-483)
- Kaltofen E and Lobo A Factoring high-degree polynomials by the black box Berlekamp algorithm Proceedings of the international symposium on Symbolic and algebraic computation, (90-98)
- Cleary J, Gomes F, Unger B, Xiao Z and Thudt R Cost of state saving & rollback Proceedings of the eighth workshop on Parallel and distributed simulation, (94-101)
- Reid-Miller M List ranking and list scan on the Cray C-90 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures, (104-113)
- Reinhold M Cache performance of garbage-collected programs Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation, (206-217)
- Nicol D, Greenberg A and Lubachevsky B (1994). Massively Parallel Algorithms for Trace-Driven Cache Simulations, IEEE Transactions on Parallel and Distributed Systems, 5:8, (849-859), Online publication date: 1-Aug-1994.
- De Micheli G (1994). Computer-Aided Hardware-Software Codesign, IEEE Micro, 14:4, (10-16), Online publication date: 1-Aug-1994.
- Deering M, Schlapp S and Lavelle M FBRAM Proceedings of the 21st annual conference on Computer graphics and interactive techniques, (167-174)
- Navarro J, Juan T and Lang T MOB forms Proceedings of the 8th international conference on Supercomputing, (354-363)
- Cleary J, Gomes F, Unger B, Xiao Z and Thudt R (1994). Cost of state saving & rollback, ACM SIGSIM Simulation Digest, 24:1, (94-101), Online publication date: 1-Jul-1994.
- Reistad B and Gifford D (1994). Static dependent costs for estimating execution time, ACM SIGPLAN Lisp Pointers, VII:3, (65-78), Online publication date: 1-Jul-1994.
- Reistad B and Gifford D Static dependent costs for estimating execution time Proceedings of the 1994 ACM conference on LISP and functional programming, (65-78)
- Sproull R, Sutherland I and Molnar C (1994). The Counterflow Pipeline Processor Architecture, IEEE Design & Test, 11:3, (48-59), Online publication date: 1-Jul-1994.
- Bhagwati V and Devadas S Automatic verification of pipelined microprocessors Proceedings of the 31st annual Design Automation Conference, (603-608)
- Casavant A MIST—a design aid for programmable pipelined processors Proceedings of the 31st annual Design Automation Conference, (532-536)
- Reinhold M (1994). Cache performance of garbage-collected programs, ACM SIGPLAN Notices, 29:6, (206-217), Online publication date: 1-Jun-1994.
- Poursepanj A (1994). The PowerPC performance modeling methodology, Communications of the ACM, 37:6, (47-55), Online publication date: 1-Jun-1994.
- Cox M and Hanrahan P (1994). A Distributed Snooping Algorithm for Pixel Merging, IEEE Parallel & Distributed Technology: Systems & Technology, 2:2, (30-36), Online publication date: 1-Jun-1994.
- Abnous A and Bagherzadeh N (1994). Pipelining and Bypassing in a VLIW Processor, IEEE Transactions on Parallel and Distributed Systems, 5:6, (658-664), Online publication date: 1-Jun-1994.
- Saxena N and McCluskey E (1994). Linear Complexity Assertions for Sorting, IEEE Transactions on Software Engineering, 20:6, (424-431), Online publication date: 1-Jun-1994.
- Torrellas J, Lam H and Hennessy J (1994). False Sharing and Spatial Locality in Multiprocessor Caches, IEEE Transactions on Computers, 43:6, (651-663), Online publication date: 1-Jun-1994.
- Drapeau A, Patterson D and Katz R (1994). Toward workload characterization of video server and digital library applications (extended abstract), ACM SIGMETRICS Performance Evaluation Review, 22:1, (274-275), Online publication date: 1-May-1994.
- Temam O, Fricker C and Jalby W (1994). Cache interference phenomena, ACM SIGMETRICS Performance Evaluation Review, 22:1, (261-271), Online publication date: 1-May-1994.
- Kotz D and Crow P (1994). The expected lifetime of “single-address-space” operating systems, ACM SIGMETRICS Performance Evaluation Review, 22:1, (161-170), Online publication date: 1-May-1994.
- Dahlin M, Mather C, Wang R, Anderson T and Patterson D (1994). A quantitative analysis of cache policies for scalable network file systems, ACM SIGMETRICS Performance Evaluation Review, 22:1, (150-160), Online publication date: 1-May-1994.
- Drapeau A, Patterson D and Katz R Toward workload characterization of video server and digital library applications (extended abstract) Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems, (274-275)
- Temam O, Fricker C and Jalby W Cache interference phenomena Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems, (261-271)
- Kotz D and Crow P The expected lifetime of “single-address-space” operating systems Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems, (161-170)
- Dahlin M, Mather C, Wang R, Anderson T and Patterson D A quantitative analysis of cache policies for scalable network file systems Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems, (150-160)
- Chen C and Somani A A unified architectural tradeoff methodology Proceedings of the 21st annual international symposium on Computer architecture, (348-357)
- Kuskin J, Ofelt D, Heinrich M, Heinlein J, Simoni R, Gharachorloo K, Chapin J, Nakahira D, Baxter J, Horowitz M, Gupta A, Rosenblum M and Hennessy J The Stanford FLASH multiprocessor Proceedings of the 21st annual international symposium on Computer architecture, (302-313)
- Nayfeh B and Olukotun K Exploring the design space for a shared-cache multiprocessor Proceedings of the 21st annual international symposium on Computer architecture, (166-175)
- Singhal A and Goldberg A Architectural support for performance tuning Proceedings of the 21st annual international symposium on Computer architecture, (48-59)
- Palacharla S and Kessler R Evaluating stream buffers as a secondary cache replacement Proceedings of the 21st annual international symposium on Computer architecture, (24-33)
- Talcott A, Yamamoto W, Serrano M, Wood R and Nemirovsky M The impact of unresolved branches on branch prediction scheme performance Proceedings of the 21st annual international symposium on Computer architecture, (12-21)
- Chen C and Somani A (1994). A unified architectural tradeoff methodology, ACM SIGARCH Computer Architecture News, 22:2, (348-357), Online publication date: 1-Apr-1994.
- Kuskin J, Ofelt D, Heinrich M, Heinlein J, Simoni R, Gharachorloo K, Chapin J, Nakahira D, Baxter J, Horowitz M, Gupta A, Rosenblum M and Hennessy J (1994). The Stanford FLASH multiprocessor, ACM SIGARCH Computer Architecture News, 22:2, (302-313), Online publication date: 1-Apr-1994.
- Nayfeh B and Olukotun K (1994). Exploring the design space for a shared-cache multiprocessor, ACM SIGARCH Computer Architecture News, 22:2, (166-175), Online publication date: 1-Apr-1994.
- Singhal A and Goldberg A (1994). Architectural support for performance tuning, ACM SIGARCH Computer Architecture News, 22:2, (48-59), Online publication date: 1-Apr-1994.
- Palacharla S and Kessler R (1994). Evaluating stream buffers as a secondary cache replacement, ACM SIGARCH Computer Architecture News, 22:2, (24-33), Online publication date: 1-Apr-1994.
- Talcott A, Yamamoto W, Serrano M, Wood R and Nemirovsky M (1994). The impact of unresolved branches on branch prediction scheme performance, ACM SIGARCH Computer Architecture News, 22:2, (12-21), Online publication date: 1-Apr-1994.
- Kuskin J, Ofelt D, Heinrich M, Heinlein J, Simoni R, Gharachorloo K, Chapin J, Nakahira D, Baxter J, Horowitz M, Gupta A, Rosenblum M and Hennessy J (1994). The Stanford FLASH multiprocessor, ACM SIGARCH Computer Architecture News, 22:2, (302-313), Online publication date: 1-Apr-1994.
- Markatos E and LeBlanc T (1994). Using Processor Affinity in Loop Scheduling on Shared-Memory Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, 5:4, (379-400), Online publication date: 1-Apr-1994.
- Upadhyaya S and Ramamurthy B (1994). Concurrent Process Monitoring with No Reference Signatures, IEEE Transactions on Computers, 43:4, (475-480), Online publication date: 1-Apr-1994.
- Magagnosc D (1994). Simulation in computer organization, ACM SIGCSE Bulletin, 26:1, (178-182), Online publication date: 12-Mar-1994.
- Magagnosc D Simulation in computer organization Proceedings of the twenty-fifth SIGCSE symposium on Computer science education, (178-182)
- Mendlson A, Pinter S and Shtokhamer R (1994). Compile time instruction cache optimizations, ACM SIGARCH Computer Architecture News, 22:1, (44-51), Online publication date: 1-Mar-1994.
- Ruemmler C and Wilkes J (1994). An introduction to disk drive modeling, Computer, 27:3, (17-28), Online publication date: 1-Mar-1994.
- Linder D and Harden J (1994). Access Graphs, IEEE Transactions on Parallel and Distributed Systems, 5:1, (39-52), Online publication date: 1-Jan-1994.
- Delic G (1993). Performance Attributes for Code and Workload Analysis On Cray X-Mp and Y-Mp Systems, International Journal of High Performance Computing Applications, 7:4, (304-336), Online publication date: 1-Dec-1993.
- Huang I and Despain A An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors Proceedings of the 26th annual international symposium on Microarchitecture, (236-246)
- Drach N and Seznec A MIDEE Proceedings of the 26th annual international symposium on Microarchitecture, (193-201)
- Franklin M and Pan T Clocked and asynchronous instruction pipelines Proceedings of the 26th annual international symposium on Microarchitecture, (177-184)
- Farrens M, Ng P and Nico P A comparision of superscalar and decoupled access/execute architectures Proceedings of the 26th annual international symposium on Microarchitecture, (100-103)
- Srivastava A and Despain A Prophetic branches Proceedings of the 26th annual international symposium on Microarchitecture, (94-99)
- Wolfe A and Boleyn R Two-ported cache alternatives for superscalar processors Proceedings of the 26th annual international symposium on Microarchitecture, (41-48)
- Pasquale B and Polyzos G A static analysis of I/O characteristics of scientific applications in a production workload Proceedings of the 1993 ACM/IEEE conference on Supercomputing, (388-397)
- Yang Q (1993). Introducing a New Cache Design into Vector Computers, IEEE Transactions on Computers, 42:12, (1411-1424), Online publication date: 1-Dec-1993.
- Cox M and Hanrahan P Pixel merging for object-parallel rendering Proceedings of the 1993 symposium on Parallel rendering, (49-56)
- Thomborson C (1993). Does your workstation computation belong on a vector supercomputer?, Communications of the ACM, 36:11, (41-ff.), Online publication date: 1-Nov-1993.
- Hillis W and Tucker L (1993). The CM-5 Connection Machine, Communications of the ACM, 36:11, (31-40), Online publication date: 1-Nov-1993.
- Ning Q Register allocation for optimal loop scheduling Proceedings of the 1993 conference of the Centre for Advanced Studies on Collaborative research: distributed computing - Volume 2, (942-955)
- Bernecky R (1993). The role of APL and J in high-performance computation, ACM SIGAPL APL Quote Quad, 24:1, (17-32), Online publication date: 1-Sep-1993.
- Bernecky R The role of APL and J in high-performance computation Proceedings of the international conference on APL, (17-32)
- Juurlink B and Wijshoff H Experiences with a model for parallel computation Proceedings of the twelfth annual ACM symposium on Principles of distributed computing, (87-96)
- White S, Hester P, Kemp J and McWilliams G (1993). How Does Processor MHz Relate to End-User Performance? Part 2, IEEE Micro, 13:5, (79-89), Online publication date: 1-Sep-1993.
- Awaga M and Takahashi H (1993). The μVP 64-Bit Vector Coprocessor, IEEE Micro, 13:5, (24-36), Online publication date: 1-Sep-1993.
- Hua K, Liu L and Peir J (1993). Designing High-Performance Processors Using Real Address Prediction, IEEE Transactions on Computers, 42:9, (1146-1151), Online publication date: 1-Sep-1993.
- Dally W (1993). A universal parallel computer architecture, New Generation Computing, 11:3-4, (227-249), Online publication date: 1-Sep-1993.
- Hashimoto T, Murakami K, Hironaka T and Yasuura H A micro-vectorprocessor architecture Proceedings of the 7th international conference on Supercomputing, (308-317)
- Kodama Y, Koumura Y, Sato M, Sakane H, Sakai S and Yamaguchi Y EMC-Y Proceedings of the 7th international conference on Supercomputing, (167-174)
- Attiya H, Chaudhuri S, Friedman R and Welch J Shared memory consistency conditions for non-sequential execution Proceedings of the fifth annual ACM symposium on Parallel Algorithms and Architectures, (241-250)
- Czeck E and Feldman J (1993). On defusing a small landmine in the type casting of pointers in the “C” language, ACM SIGPLAN Notices, 28:8, (53-56), Online publication date: 1-Aug-1993.
- Culler D, Karp R, Patterson D, Sahay A, Schauser K, Santos E, Subramonian R and von Eicken T LogP: towards a realistic model of parallel computation Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming, (1-12)
- Ball T and Larus J Branch prediction for free Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation, (300-313)
- Kolte P and Harrold M Load/store range analysis for global register allocation Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation, (268-277)
- Boyd M and Whalley D Isolation and analysis of optimization errors Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation, (26-35)
- Eickemeyer R and Vassiliadis S (1993). A load-instruction unit for pipelined processors, IBM Journal of Research and Development, 37:4, (547-564), Online publication date: 1-Jul-1993.
- Bailey M, Pagels M and Wong K (1993). How using busses in multicomputer programs affects conservative parallel simulation, ACM SIGSIM Simulation Digest, 23:1, (93-100), Online publication date: 1-Jul-1993.
- Culler D, Karp R, Patterson D, Sahay A, Schauser K, Santos E, Subramonian R and von Eicken T (1993). LogP: towards a realistic model of parallel computation, ACM SIGPLAN Notices, 28:7, (1-12), Online publication date: 1-Jul-1993.
- Bailey M, Pagels M and Wong K How using busses in multicomputer programs affects conservative parallel simulation Proceedings of the seventh workshop on Parallel and distributed simulation, (93-100)
- Gupta R and De Micheli G (1993). Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test, 10:3, (29-41), Online publication date: 1-Jul-1993.
- Russell G and Shaw P (1993). Shifting Register Windows, IEEE Micro, 13:4, (28-34), Online publication date: 1-Jul-1993.
- Graf H, Sackinger E and Jackel L (1993). Recent developments of electronic neural nets in North America, Journal of VLSI Signal Processing Systems, 6:1, (19-31), Online publication date: 1-Jun-1993.
- Ball T and Larus J (1993). Branch prediction for free, ACM SIGPLAN Notices, 28:6, (300-313), Online publication date: 1-Jun-1993.
- Kolte P and Harrold M (1993). Load/store range analysis for global register allocation, ACM SIGPLAN Notices, 28:6, (268-277), Online publication date: 1-Jun-1993.
- Boyd M and Whalley D (1993). Isolation and analysis of optimization errors, ACM SIGPLAN Notices, 28:6, (26-35), Online publication date: 1-Jun-1993.
- Sugumar R and Abraham S (1993). Efficient simulation of caches under optimal replacement with applications to miss characterization, ACM SIGMETRICS Performance Evaluation Review, 21:1, (24-35), Online publication date: 1-Jun-1993.
- Sugumar R and Abraham S Efficient simulation of caches under optimal replacement with applications to miss characterization Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems, (24-35)
- Seznec A A case for two-way skewed-associative caches Proceedings of the 20th annual international symposium on computer architecture, (169-178)
- Hidaka Y, Koike H and Tanaka H Multiple threads in cyclic register windows Proceedings of the 20th annual international symposium on computer architecture, (131-142)
- Waldspurger C and Weihl W Register relocation Proceedings of the 20th annual international symposium on computer architecture, (120-130)
- Nagle D, Uhlig R, Stanley T, Sechrest S, Mudge T and Brown R Design tradeoffs for software-managed TLBs Proceedings of the 20th annual international symposium on computer architecture, (27-38)
- Ewy B and Evans J (1993). Secondary cache performance in RISC architecture, ACM SIGARCH Computer Architecture News, 21:3, (34-37), Online publication date: 1-Jun-1993.
- Ramanathan G and Oren J (1993). Survey of commercial parallel machines, ACM SIGARCH Computer Architecture News, 21:3, (13-33), Online publication date: 1-Jun-1993.
- Uht A (1993). Extraction of massive instruction level parallelism, ACM SIGARCH Computer Architecture News, 21:3, (5-12), Online publication date: 1-Jun-1993.
- Seznec A (1993). A case for two-way skewed-associative caches, ACM SIGARCH Computer Architecture News, 21:2, (169-178), Online publication date: 1-May-1993.
- Hidaka Y, Koike H and Tanaka H (1993). Multiple threads in cyclic register windows, ACM SIGARCH Computer Architecture News, 21:2, (131-142), Online publication date: 1-May-1993.
- Waldspurger C and Weihl W (1993). Register relocation, ACM SIGARCH Computer Architecture News, 21:2, (120-130), Online publication date: 1-May-1993.
- Nagle D, Uhlig R, Stanley T, Sechrest S, Mudge T and Brown R (1993). Design tradeoffs for software-managed TLBs, ACM SIGARCH Computer Architecture News, 21:2, (27-38), Online publication date: 1-May-1993.
- Smith R, Archibald J and Nelson B (1993). Evaluating performance of prefetching second level caches, ACM SIGMETRICS Performance Evaluation Review, 20:4, (31-42), Online publication date: 1-May-1993.
- Redinbo G, Napolitano L and Andaleon D (1993). Multibit Correcting Data Interface for Fault-Tolerant Systems, IEEE Transactions on Computers, 42:4, (433-446), Online publication date: 1-Apr-1993.
- Ullah N and Holle M (1993). The MC88110 implementation of precise exceptions in a superscalar architecture, ACM SIGARCH Computer Architecture News, 21:1, (15-25), Online publication date: 1-Mar-1993.
- Athanas P and Silverman H (1993). Processor reconfiguration through instruction-set metamorphosis, Computer, 26:3, (11-18), Online publication date: 1-Mar-1993.
- Christopher W, Procter S and Anderson T The Nachos instructional operating system Proceedings of the USENIX Winter 1993 Conference Proceedings on USENIX Winter 1993 Conference Proceedings, (4-4)
- Torng H and Day M (1993). Interrupt Handling for Out-of-Order Execution Processors, IEEE Transactions on Computers, 42:1, (122-127), Online publication date: 1-Jan-1993.
- Papachristou C and Immaneni V (1993). Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing, IEEE Transactions on Computers, 42:1, (45-61), Online publication date: 1-Jan-1993.
- Kato T, Ono T and Bagherzadeh N Performance analysis and design methodology for a scalable superscalar architecture Proceedings of the 25th annual international symposium on Microarchitecture, (246-255)
- Franklin M and Sohi G Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors Proceedings of the 25th annual international symposium on Microarchitecture, (236-245)
- Wilken K and Goodwin D Toward zero-cost branches using instruction registers Proceedings of the 25th annual international symposium on Microarchitecture, (214-217)
- Knieser M and Papachristou C Y-Pipe Proceedings of the 25th annual international symposium on Microarchitecture, (125-128)
- Wolfe A and Chanin A Executing compressed programs on an embedded RISC architecture Proceedings of the 25th annual international symposium on Microarchitecture, (81-91)
- Kato T, Ono T and Bagherzadeh N (1992). Performance analysis and design methodology for a scalable superscalar architecture, ACM SIGMICRO Newsletter, 23:1-2, (246-255), Online publication date: 10-Dec-1992.
- Franklin M and Sohi G (1992). Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors, ACM SIGMICRO Newsletter, 23:1-2, (236-245), Online publication date: 10-Dec-1992.
- Wilken K and Goodwin D (1992). Toward zero-cost branches using instruction registers, ACM SIGMICRO Newsletter, 23:1-2, (214-217), Online publication date: 10-Dec-1992.
- Knieser M and Papachristou C (1992). Y-Pipe, ACM SIGMICRO Newsletter, 23:1-2, (125-128), Online publication date: 10-Dec-1992.
- Wolfe A and Chanin A (1992). Executing compressed programs on an embedded RISC architecture, ACM SIGMICRO Newsletter, 23:1-2, (81-91), Online publication date: 10-Dec-1992.
- Chen Y and Veidenbaum A An effective write policy for software coherence schemes Proceedings of the 1992 ACM/IEEE conference on Supercomputing, (661-672)
- Taylor V Sparse matrix computations Proceedings of the 1992 ACM/IEEE conference on Supercomputing, (598-607)
- Tyagi A VLSI design parsing (preliminary version) Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, (30-34)
- Hill M, Larus J, Reinhardt S and Wood D (1992). Cooperative shared memory, ACM SIGPLAN Notices, 27:9, (262-273), Online publication date: 1-Sep-1992.
- Chiueh T and Katz R (1992). Eliminating the address translation bottleneck for physical address cache, ACM SIGPLAN Notices, 27:9, (137-148), Online publication date: 1-Sep-1992.
- Hill M, Larus J, Reinhardt S and Wood D Cooperative shared memory Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, (262-273)
- Chiueh T and Katz R Eliminating the address translation bottleneck for physical address cache Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, (137-148)
- Esponda M and Rojas R (1992). A graphical comparison of RISC processors, ACM SIGARCH Computer Architecture News, 20:4, (2-8), Online publication date: 1-Sep-1992.
- Wang Y, Mangaser A and Srinivasan P (1992). A Processor Architecture for 3D Graphics, IEEE Computer Graphics and Applications, 12:5, (96-105), Online publication date: 1-Sep-1992.
- Stone H, Turek J and Wolf J (1992). Optimal Partitioning of Cache Memory, IEEE Transactions on Computers, 41:9, (1054-1068), Online publication date: 1-Sep-1992.
- Gurd J and Snelling D Manchester data-flow Proceedings of the 6th international conference on Supercomputing, (216-225)
- Bell G (1992). Ultracomputers: a teraflop before its time, Communications of the ACM, 35:8, (26-47), Online publication date: 1-Aug-1992.
- Prabhu U and Prangrle B Superpipelined control and data path synthesis Proceedings of the 29th ACM/IEEE Design Automation Conference, (638-643)
- Gupta R, Coelho C and De Micheli G Synthesis and simulation of digital systems containing interacting hardware and software components Proceedings of the 29th ACM/IEEE Design Automation Conference, (225-230)
- Seawright A and Brewer F Synthesis from production-based specifications Proceedings of the 29th ACM/IEEE Design Automation Conference, (194-199)
- Mueller F and Whalley D (1992). Avoiding unconditional jumps by code replication, ACM SIGPLAN Notices, 27:7, (322-330), Online publication date: 1-Jul-1992.
- Sosič R (1992). Dynascope, ACM SIGPLAN Notices, 27:7, (12-21), Online publication date: 1-Jul-1992.
- Mueller F and Whalley D Avoiding unconditional jumps by code replication Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation, (322-330)
- Sosič R Dynascope Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation, (12-21)
- Leighton T Methods for message routing in parallel machines Proceedings of the twenty-fourth annual ACM symposium on Theory of Computing, (77-96)
- Bartal Y, Fiat A and Rabani Y Competitive algorithms for distributed data management (extended abstract) Proceedings of the twenty-fourth annual ACM symposium on Theory of Computing, (39-50)
- Whalley D (1992). Fast instruction cache performance evaluation using compile-time analysis, ACM SIGMETRICS Performance Evaluation Review, 20:1, (13-22), Online publication date: 1-Jun-1992.
- Chevance R (1992). An evaluation methodology for microprocessor and system architecture, ACM SIGARCH Computer Architecture News, 20:3, (4-13), Online publication date: 1-Jun-1992.
- Leiserson C, Abuhamdeh Z, Douglas D, Feynman C, Ganmukhi M, Hill J, Hillis D, Kuszmaul B, St. Pierre M, Wells D, Wong M, Yang S and Zak R The network architecture of the Connection Machine CM-5 (extended abstract) Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures, (272-285)
- Whalley D Fast instruction cache performance evaluation using compile-time analysis Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, (13-22)
- Talluri M, Kong S, Hill M and Patterson D Tradeoffs in supporting two page sizes Proceedings of the 19th annual international symposium on Computer architecture, (415-424)
- Yang Q and Yang L A novel cache design for vector processing Proceedings of the 19th annual international symposium on Computer architecture, (362-371)
- De Gloria A and Faraboschi P Instruction-level parallelism in Prolog Proceedings of the 19th annual international symposium on Computer architecture, (224-233)
- Olukotun K, Mudge T and Brown R Performance optimization of pipelined primary cache Proceedings of the 19th annual international symposium on Computer architecture, (181-190)
- Intrater G and Spillinger I Performance evaluation of a decoded instruction cache for variable instruction-length computers Proceedings of the 19th annual international symposium on Computer architecture, (106-113)
- Gharachorloo K, Gupta A and Hennessy J Hiding memory latency using dynamic scheduling in shared-memory multiprocessors Proceedings of the 19th annual international symposium on Computer architecture, (22-33)
- Talluri M, Kong S, Hill M and Patterson D (1992). Tradeoffs in supporting two page sizes, ACM SIGARCH Computer Architecture News, 20:2, (415-424), Online publication date: 1-May-1992.
- Yang Q and Yang L (1992). A novel cache design for vector processing, ACM SIGARCH Computer Architecture News, 20:2, (362-371), Online publication date: 1-May-1992.
- De Gloria A and Faraboschi P (1992). Instruction-level parallelism in Prolog, ACM SIGARCH Computer Architecture News, 20:2, (224-233), Online publication date: 1-May-1992.
- Olukotun K, Mudge T and Brown R (1992). Performance optimization of pipelined primary cache, ACM SIGARCH Computer Architecture News, 20:2, (181-190), Online publication date: 1-May-1992.
- Intrater G and Spillinger I (1992). Performance evaluation of a decoded instruction cache for variable instruction-length computers, ACM SIGARCH Computer Architecture News, 20:2, (106-113), Online publication date: 1-May-1992.
- Gharachorloo K, Gupta A and Hennessy J (1992). Hiding memory latency using dynamic scheduling in shared-memory multiprocessors, ACM SIGARCH Computer Architecture News, 20:2, (22-33), Online publication date: 1-May-1992.
- Keown W, Koopman P and Collins A (1992). Real-time performance of the HARRIS RTX 2000 stack architecture versus the Sun 4 SPARC and the Sun 3 M68020 architectures with a proposed real-time performance benchmark, ACM SIGMETRICS Performance Evaluation Review, 19:4, (40-48), Online publication date: 1-May-1992.
- Czeck E and Siewiorek D (1992). Observations on the Effects of Fault Manifestation as a Function of Workload, IEEE Transactions on Computers, 41:5, (559-566), Online publication date: 1-May-1992.
- Wood J and Grossman H Interprocedural register allocation for RISC machines Proceedings of the 30th annual ACM Southeast Regional Conference, (188-195)
- Davidson J, Rabung J and Whalley D (1992). Solutions Relating Static and Dynamic Machine Code Measurements, IEEE Transactions on Computers, 41:4, (444-454), Online publication date: 1-Apr-1992.
- Davidson J and Holler A (1992). Subprogram Inlining, IEEE Transactions on Software Engineering, 18:2, (89-102), Online publication date: 1-Feb-1992.
- Dahlgren F and Stenström P On reconfigurable on-chip data caches Proceedings of the 24th annual international symposium on Microarchitecture, (189-198)
- Miller W, Najjar W and Böhm A A quantitative analysis of locality in dataflow programs Proceedings of the 24th annual international symposium on Microarchitecture, (12-18)
- Taylor V, Ranade A and Messerschmitt D Three-dimensional finite-element analyses Proceedings of the 1991 ACM/IEEE conference on Supercomputing, (786-795)
- Corporaal H and Mulder H MOVE: a framework for high-performance processor design Proceedings of the 1991 ACM/IEEE conference on Supercomputing, (692-701)
- Miller E and Katz R Input/output behavior of supercomputing applications Proceedings of the 1991 ACM/IEEE conference on Supercomputing, (567-576)
- Baer J and Chen T An effective on-chip preloading scheme to reduce data access penalty Proceedings of the 1991 ACM/IEEE conference on Supercomputing, (176-186)
- Burch J Using BDDs to verify multipliers Proceedings of the 28th ACM/IEEE Design Automation Conference, (408-412)
- Proebsting T and Fischer C (1991). Linear-time, optimal code scheduling for delayed-load architectures, ACM SIGPLAN Notices, 26:6, (256-267), Online publication date: 1-Jun-1991.
- Jain S (1991). Circular scheduling, ACM SIGPLAN Notices, 26:6, (219-228), Online publication date: 1-Jun-1991.
- Akella J and Siewiorek D (1991). Modeling and measurement of the impact of Input/Output on system performance, ACM SIGARCH Computer Architecture News, 19:3, (390-399), Online publication date: 1-May-1991.
- Stephens C, Cogswell B, Heinlein J, Palmer G and Shen J (1991). Instruction level profiling and evaluation of the IBM/6000, ACM SIGARCH Computer Architecture News, 19:3, (180-189), Online publication date: 1-May-1991.
- Vajapeyam S, Sohi G and Hsu W (1991). An empirical study of the CRAY Y-MP processor using the Perfect club benchmarks, ACM SIGARCH Computer Architecture News, 19:3, (170-179), Online publication date: 1-May-1991.
- Olukotun O, Mudge T and Brown R (1991). Implementing a cache for a high-performance GaAs microprocessor, ACM SIGARCH Computer Architecture News, 19:3, (138-147), Online publication date: 1-May-1991.
- Proebsting T and Fischer C Linear-time, optimal code scheduling for delayed-load architectures Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, (256-267)
- Jain S Circular scheduling Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, (219-228)
- Mangione-Smith W, Abraham S and Davidson E (1991). Vector register design for polycyclic vector scheduling, ACM SIGARCH Computer Architecture News, 19:2, (154-163), Online publication date: 2-Apr-1991.
- Hall C and O'Brien K (1991). Performance characteristics of architectural features of the IBM RISC System/6000, ACM SIGARCH Computer Architecture News, 19:2, (303-309), Online publication date: 2-Apr-1991.
- Cmelik R, Kong S, Ditzel D and Kelly E (1991). An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks, ACM SIGARCH Computer Architecture News, 19:2, (290-302), Online publication date: 2-Apr-1991.
- Benitez M and Davidson J (1991). Code generation for streaming: an access/execute mechanism, ACM SIGARCH Computer Architecture News, 19:2, (132-141), Online publication date: 2-Apr-1991.
- Bradlee D, Eggers S and Henry R (1991). Integrating register allocation and instruction scheduling for RISCs, ACM SIGARCH Computer Architecture News, 19:2, (122-131), Online publication date: 2-Apr-1991.
- Mangione-Smith W, Abraham S and Davidson E (1991). Vector register design for polycyclic vector scheduling, ACM SIGOPS Operating Systems Review, 25:Special Issue, (154-163), Online publication date: 2-Apr-1991.
- Hall C and O'Brien K (1991). Performance characteristics of architectural features of the IBM RISC System/6000, ACM SIGOPS Operating Systems Review, 25:Special Issue, (303-309), Online publication date: 2-Apr-1991.
- Cmelik R, Kong S, Ditzel D and Kelly E (1991). An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks, ACM SIGOPS Operating Systems Review, 25:Special Issue, (290-302), Online publication date: 2-Apr-1991.
- Benitez M and Davidson J (1991). Code generation for streaming: an access/execute mechanism, ACM SIGOPS Operating Systems Review, 25:Special Issue, (132-141), Online publication date: 2-Apr-1991.
- Bradlee D, Eggers S and Henry R (1991). Integrating register allocation and instruction scheduling for RISCs, ACM SIGOPS Operating Systems Review, 25:Special Issue, (122-131), Online publication date: 2-Apr-1991.
- Mangione-Smith W, Abraham S and Davidson E (1991). Vector register design for polycyclic vector scheduling, ACM SIGPLAN Notices, 26:4, (154-163), Online publication date: 2-Apr-1991.
- Hall C and O'Brien K (1991). Performance characteristics of architectural features of the IBM RISC System/6000, ACM SIGPLAN Notices, 26:4, (303-309), Online publication date: 2-Apr-1991.
- Cmelik R, Kong S, Ditzel D and Kelly E (1991). An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks, ACM SIGPLAN Notices, 26:4, (290-302), Online publication date: 2-Apr-1991.
- Benitez M and Davidson J (1991). Code generation for streaming: an access/execute mechanism, ACM SIGPLAN Notices, 26:4, (132-141), Online publication date: 2-Apr-1991.
- Bradlee D, Eggers S and Henry R (1991). Integrating register allocation and instruction scheduling for RISCs, ACM SIGPLAN Notices, 26:4, (122-131), Online publication date: 2-Apr-1991.
- Seeger B and Larson P (1991). Multi-disk B-trees, ACM SIGMOD Record, 20:2, (436-445), Online publication date: 1-Apr-1991.
- Akella J and Siewiorek D Modeling and measurement of the impact of Input/Output on system performance Proceedings of the 18th annual international symposium on Computer architecture, (390-399)
- Stephens C, Cogswell B, Heinlein J, Palmer G and Shen J Instruction level profiling and evaluation of the IBM/6000 Proceedings of the 18th annual international symposium on Computer architecture, (180-189)
- Vajapeyam S, Sohi G and Hsu W An empirical study of the CRAY Y-MP processor using the Perfect club benchmarks Proceedings of the 18th annual international symposium on Computer architecture, (170-179)
- Olukotun O, Mudge T and Brown R Implementing a cache for a high-performance GaAs microprocessor Proceedings of the 18th annual international symposium on Computer architecture, (138-147)
- Seeger B and Larson P Multi-disk B-trees Proceedings of the 1991 ACM SIGMOD international conference on Management of data, (436-445)
- Mangione-Smith W, Abraham S and Davidson E Vector register design for polycyclic vector scheduling Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, (154-163)
- Hall C and O'Brien K Performance characteristics of architectural features of the IBM RISC System/6000 Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, (303-309)
- Cmelik R, Kong S, Ditzel D and Kelly E An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, (290-302)
- Benitez M and Davidson J Code generation for streaming: an access/execute mechanism Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, (132-141)
- Bradlee D, Eggers S and Henry R Integrating register allocation and instruction scheduling for RISCs Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, (122-131)
- Sijstermans F and van der Meer J (1991). CD-I full-motion video encoding on a parallel computer, Communications of the ACM, 34:4, (81-91), Online publication date: 1-Apr-1991.
- Oyang Y, Wen C, Chen Y and Lin S (1990). The effect of employing advanced branching mechanisms in superscalar processors, ACM SIGARCH Computer Architecture News, 18:4, (35-52), Online publication date: 2-Dec-1990.
- Ginosar R and Michell N (1990). On the potential of asynchronous pipelined processors, ACM SIGARCH Computer Architecture News, 18:4, (27-34), Online publication date: 2-Dec-1990.
- Holler M VLSI implementations of learning and memory systems Proceedings of the 4th International Conference on Neural Information Processing Systems, (993-1000)
- Przybylski S (1990). The performance impact of block sizes and fetch strategies, ACM SIGARCH Computer Architecture News, 18:2SI, (160-169), Online publication date: 1-Jun-1990.
- Przybylski S The performance impact of block sizes and fetch strategies Proceedings of the 17th annual international symposium on Computer Architecture, (160-169)
Index Terms
- Computer architecture: a quantitative approach
Please enable JavaScript to view thecomments powered by Disqus.
Recommendations
High-Level Computer Architecture
Associated with each programming language is a computer architecture that executes programs in that language. If the language is a low-level instruction set, the associated computer architecture is a low-level von Neumann architecture; if the language ...