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MIST—a design aid for programmable pipelined processors

Published: 06 June 1994 Publication History
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References

[1]
J. L. Hennessy and D. A. Patterson, Computer Architecture A Quantitative Approach. Morgan Kaufmann Publishers, Inc., 1990.
[2]
G. Kane and J. Heinrich, MIPS RISC Architecture. Prentice Hall, Englewood Cliffs, NJ, 1992.
[3]
P. Paulin and J. Knight, "Force-Directed Scheduling in Automatic Data Path Synthesis," in 24th Design Automation Conference, pp. 195-202, 1987.
[4]
C.-T. Hwang, Y.-C. Hsu, and Y.-L. Lin, "Scheduling for Functional Pipelining and Loop Winding," in 28th Design Automation Conference, pp. 764-769, 1991.
[5]
M. Nourani and C. Papachristou, "Moving Frame Scheduling and Mixed Scheduling-Allocation for Automated Synthesis of Digital Systems," in 29th Design Automation Conference, pp. 99-105, 1992.
[6]
R.J. Cloutier and D. E. Thomas, "Synthesis of Pipelined Instruction Set Processors," in 30th Design Automation Conference, pp. 583-588, 1993.
[7]
R.M. Tomosulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development, vol. 11, no. 1, pp. 25-33, 1967.
[8]
G.L. Nemhauser and L. A. Wolsey, Integer and Combinatorial Optimization. Wiley Interscience, 1988.
[9]
M.W. Padberg, "On the Facial Structure of Set Packing Polyhedra," Mathematical Programming, vol. 5, pp. 199-215, 1973.
[10]
G.L. Nemhauser and G. Sigismondi, "A Strong Cutting Plane/Branchand-Bound Algorithm for Node Packing," tech. rep., School of Industrial and Systems Engineering, Georgia Institute of Technology, 1989.
[11]
C. H. Gebotys and M. I. Elmasry, Optimal VLSI Architectural Synthesis: Area, Performance, Testability. Kluwer Academic Publishers, 1992.
[12]
V. Peng, S. S., and G. M., "On the Implementation of Shifters, Multipliers, and Dividers in VLSI Floating Point Units," in 8th Symposium on Computer Arithmetic, pp. 95-102, 1987.
[13]
D. Goldberg, Computer Architecture A Quantitative Approach, ch. Computer Arithmetic, pp. A1-A66. Morgan Kaufmann Publishers, Inc., 1990.
[14]
W.M. McAllister and D. Zuras, "An NMOS 64b Floating-Point Chip Set," in ISSCC 86, pp. 34-35, 1986.
[15]
J. Gosling, "Some Tricks of the (Floating-Point) Trade," in 6th Symposium on Computer Arithmetic, pp. 218-220, 1983.
[16]
M.R. Santoro, G. Bewick, and M. Horowitz, "Rounding Algorithms for IEEE Multipliers," in 9th Symposium on Computer Arithmetic, pp. 176-183, 1989.
[17]
J. Fandrianto, "Algorithm for High Speed Shared Radix 4 Division and Radix 4 Square Root," in 8th Symposium on Computer Arithmetic, pp. 73-79, 1987.
[18]
J. Fandrianto, "Algorithm for High Speed Shared Radix 8 Division and Radix 8 Square Root," in 9th Symposium on Computer Arithmetic, pp. 68-75, 1989.

Cited By

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  • (1998)MatisseIEEE Design & Test10.1109/54.67920515:2(22-33)Online publication date: 1-Apr-1998
  • (1995)Balancing structural hazards and hardware cost of pipelined processorsProceedings of the 1995 European conference on Design and Test10.5555/787258.787492Online publication date: 6-Mar-1995
  • (1995)Balancing structural hazards and hardware cost of pipelined processorsProceedings the European Design and Test Conference. ED&TC 199510.1109/EDTC.1995.470344(562-566)Online publication date: 1995

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cover image ACM Conferences
DAC '94: Proceedings of the 31st annual Design Automation Conference
June 1994
739 pages
ISBN:0897916530
DOI:10.1145/196244
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 06 June 1994

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Cited By

View all
  • (1998)MatisseIEEE Design & Test10.1109/54.67920515:2(22-33)Online publication date: 1-Apr-1998
  • (1995)Balancing structural hazards and hardware cost of pipelined processorsProceedings of the 1995 European conference on Design and Test10.5555/787258.787492Online publication date: 6-Mar-1995
  • (1995)Balancing structural hazards and hardware cost of pipelined processorsProceedings the European Design and Test Conference. ED&TC 199510.1109/EDTC.1995.470344(562-566)Online publication date: 1995

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