Threaded Prefetching: A New Instruction Memory Hierarchy for Real-Time Systems

• Aho, A.V., Sethi, R. and Ullman, J.D. Compilers Principles, Techniques, and Tools. Addison-Wesley Publishing Company, Reading, MA, 1988.

  Google Scholar 

• Arnold, R., Mueller, F., Whalley, D. and Harmon, M. Bounding worst-case instruction cache performance. In Proceedings of the 15th Real-Time Systems Symposium, pages 172–181, 1994.

• Callahan, D., Kennedy, K. and Porterfield, A. Software prefetching. In Proceedings of the Fourth International Conference on Architectural Support on Programming Languages and Operating Systems, pages 40–52, 1991.

• Chen, T.-F. and Baer, J.-L. Reducing memory latency via non-blocking and prefetching caches. In Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 51–61, 1992.

• Fischer, C.N. and LeBlanc, R.J. Crafting a Compiler with C. The Benjamin/Cummings Publishing Company, Inc., Redwood City, CA, 1991.

  Google Scholar 

• Fraser, C.W. and Hanson, D.R. A code generation interface for ANSI C. Technical Report CSL-TR-270-90, Dept. of Computer Science, Princeton University, July 1990.

• Hennessy, J.L. and Patterson, D.A. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, San Mateo, CA, 1990.

  Google Scholar 

• Hilf, W. and Nausch, A. The M68000 Family Volum 1, page 48. Prentice Hall, Englewood Cliffs, NJ, 1989.

  Google Scholar 

• Hill, M.D. Aspects of Cache Memory and Instruction Buffer Performance. PhD thesis, University of California, Berkeley, Nov. 1987.

  Google Scholar 

• Intel. Microprocessors Handbook. Intel Corporation, 1990.

• Jouppi, N.P. Improving directed-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 364–373, 1990.

• Kane, G. and Heinrich, J. MIPS RISC Architecture. Prentice Hall, Englewood Cliffs, NJ, 1992.

  Google Scholar 

• Karp, R.M. A characterization of the minimum cycle mean in a digraph. Discrete Mathematics, 23:309–311, 1978.

  Google Scholar 

• Kirk, D.B. SMART (Strategic Memory Allocation for Real-Time) cache design. In Proceedings of the 10th Real-Time Systems Symposium, pages 229–237, 1989.

• Klaiber, A.C. and Levy, H.M. Architecture for software-controlled data prefetching. In Proceedings of the 18th Annual International Symposium on Computer Architecture, pages 43–63, 1991.

• Lim, S.-S., Bae, Y.H., Jang, G.T., Rhee, B.-D., Min, S.L., Park, C.Y., Shin, H., Park, K. and Kim, C.S. An accurate worst case timing analysis technique for RISC processors. In Proceedings of the 15th Real-Time Systems Symposium, pages 97–108, 1994.

• Liu, J.-C. and Lee, H.-J. Deterministic upperbounds of the worst-case execution times of cached programs. In Proceedings of the 15th Real-Time Systems Symposium, pages 182–191, 1994.

• Rau, B.R. and Rossman, G.E. The effect of instruction fetch strategies upon the performance of pipelined instruction units. In Proceedings of the 4th Annual International Symposium on Computer Architecture, pages 80–89, 1977.

• Rawat, J. Static Analysis of Cache Performance for Real-Time Programming. Master's thesis, Iowa State University, 1993.

• Shaw, R.C. Reasoning about time in higher-level language software. IEEE Transactions On Software Engineering, 15(7):875–889, July 1989.

  Google Scholar 

• Smith, A.J. Cache memories. ACM Computing Surveys, 14(3):473–530, 1982.

  Google Scholar 

• Smith, A.J. Sequential program prefetching in memory hierarchies. IEEE Computer, pages 7–21, Dec. 1978.

• Wolfe, A. Software-based cache partitioning for real-time applications. In Proceedings of the Third Workshop on Responsive Computer Systems, Sept. 1993.

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