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A standard cell based synchronous dual-bit adder with embedded carry look-ahead

Published: 30 November 2010 Publication History

Abstract

A novel synchronous dual-bit adder design, realized using the elements of commercial standard cell libraries, is presented in this article. The adder embeds two-bit carry look-ahead generator functionality and is realized using simple and compound gates of the standard cell library. The performance of the proposed dual-bit adder design is evaluated and compared vis-à-vis the conventional full adder (implemented using two half adder blocks) and the library's full adder element, when performing 32-bit addition on the basis of the fundamental carry propagate adder topology. Based on experimentations targeting the best case process corner of the high-speed 130nm UMC CMOS cell library and the highest speed corner of the inherently power optimized 65nm STMicroelectronics CMOS standard cell library, it has been found that the proposed adder module is effective in achieving significant performance gains even in comparison with the commercial library based adder whilst facilitating reduced energy-delay product.

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  • (2011)Analyzing the impact of local and global indication on a self-timed systemProceedings of the 5th European conference on European computing conference10.5555/1991016.1991032(85-91)Online publication date: 28-Apr-2011
  1. A standard cell based synchronous dual-bit adder with embedded carry look-ahead

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    cover image Guide Proceedings
    ECS'10/ECCTD'10/ECCOM'10/ECCS'10: Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science
    November 2010
    353 pages
    ISBN:9789604742509

    Publisher

    World Scientific and Engineering Academy and Society (WSEAS)

    Stevens Point, Wisconsin, United States

    Publication History

    Published: 30 November 2010

    Author Tags

    1. adder
    2. energy-delay product
    3. high speed
    4. low power
    5. power-delay product
    6. semi-custom design
    7. standard cells

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    • (2011)Analyzing the impact of local and global indication on a self-timed systemProceedings of the 5th European conference on European computing conference10.5555/1991016.1991032(85-91)Online publication date: 28-Apr-2011

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