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Multi-level texture caching for 3D graphics hardware

Authors:

Narendra Bhandari,

Michael ShantzAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 26, Issue 3

Pages 86 - 97

https://doi.org/10.1145/279361.279372

Published: 16 April 1998 Publication History

Abstract

Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval of texture during rasterization, and the application is responsible for managing this memory. The push architecture has a bandwidth advantage, but disadvantages of limited texture capacity, escalation of accelerator memory requirements (and therefore cost), and poor memory utilization. The push architecture also requires the programmer to solve the bin- packing problem of managing accelerator memory each frame. More recently graphics hardware on PC-class machines has moved to an implementation of what we call the pull architecture. Texture is stored in system memory and downloaded by the accelerator as needed. The pull architecture has advantages of texture capacity, stems the escalation of accelerator memory requirements, and has good memory utilization. It also frees the programmer from accelerator texture memory management. However, the pull architecture suffers escalating requirements for bandwidth from main memory to the accelerator. In this paper we propose multi-level texture caching to provide the accelerator with the bandwidth advantages of the push architecture combined with the capacity advantages of the pull architecture. We have studied the feasibility of 2-level caching and found the following: (1) significant re-use of texture between frames; (2) L2 caching requires significantly less memory than the push architecture; (3) L2 caching requires significantly less bandwidth from host memory than the pull architecture; (4) L2 caching enables implementation of smaller L1 caches that would otherwise bandwidth-limit accelerators on the workloads in this paper. Results suggest that an L2 cache achieves the original advantage of the pull architecture --- stemming the growth of local texture memory --- while at the same time stemming the current explosion in demand for texture bandwidth between host memory and the accelerator.

References

[1]

K. Akeley, "Reality Engine Graphics," Computer Graphics (Proc. Siggraph), August 1993, pp. 109-116.

Digital Library

[2]

J. Blinn and M. Newell, "Texture and Reflection in Computer Generated Images", Communications of the ACM, Vol. 19, No. 10, October 1976.

Digital Library

[3]

J. Blinn, "The Truth About Texture Mapping," IEEE Computer Graphics and Applications, March 1990, pp. 78 - 83.

Digital Library

[4]

E. Catmull, "'A Subdivision Algorithm for Computer Display of Curved Surfaces," Ph.D. dissertation, University of Utah, 1974.

Digital Library

[5]

F. Crow, "The Aliasing Problem in Computer Synthesized Shaded Images," Ph.D. dissertation, University of Utah, 1976.

Digital Library

[6]

F. Crow, "Summed-Area Tables for Texture Mapping," Computer Graphics (Proc. Siggraph), July 1984.

Digital Library

[7]

M. Deering, S. Schlapp, M. Lavalle, "FBRAM: A New Form of Memory Optimized for 3D Graphics," Computer Graphics (Proc. Siggraph), August 1994, pp. 167-174.

Digital Library

[8]

Y. Denville, "A low-cost usage-based replacement algorithm for cache memories," ACM Computer Architecture News, Vol. 18, No. 4, December 990, pp. 52-58.

Digital Library

[9]

E. Feibush, M. Levoy, and R. Cook, "Synthetic Texturing Using Digital Filters," Computer Graphics (Proc. Siggraph), 14, July, 1980.

Digital Library

[10]

J. Foley, A. van Dam, S. Feiner, J. Hughes, Computer Graphics: Principles and Practice, 2nd ed., Addison-Wesley, Reading MA, 1990.

Digital Library

[11]

Z. Hakura and A. Gupta, "The Design and Analysis of a Cache Architecture for Texture Mapping," Proc. of the 24th International Symposium on Computer Architecture, May 1997, pp. 108- I19.

Digital Library

[12]

P. S. Heckbert, Fundamentals of Texture Mapping and hnage Warping, Master's thesis, University of California at Berkeley, June 1989.

[13]

P. S. Heckbert and H. P. Moreton, "Interpolation for Polygon Texture Mapping and Shading." In David F. Rogers and Rae A. Eamsbaw, editors, State of the Art in Computer Graphics: Visualization and Modeling, pp. 101-111. Springer-Verlag, 1991.

[14]

B. Hook, "All 1 Want for Christmas '98 is a Hardware Accelerator that Doesn't Suck," Gam~ Developer Magazine, September 1997.

[15]

K. Hwang and F. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, New York NY, 1984.

Digital Library

[16]

Intel Corporation, Accelerated Graphics Port Interface Specification, Revision 1.0, Intel Corporation, t996.

[17]

J. Montrym, D. Bantu, D. Dignam, C. Migdal, "lnfiniteReality: A Real-Time Graphics System," Computer Graphics (Proc. Siggraph), August 1997, pp. 293-301.

Digital Library

[18]

J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufman, San Mateo CA, 1990.

Digital Library

[19]

R.N. lbbett and P.C. Capon, "The Development of the MU5 Computer System," Communications of the A CM, Vol. 21, January 1978, pp. 13 - 24,

Digital Library

[20]

D. Peachey, "Texture on Demand," unpublished manuscript, Pixar, San Rafael CA, 1990.

[21]

T. Porter and T. Duff, "'Compositing Digital Images," Computer Graphics (Proc. Siggraph), July 1984.

Digital Library

[22]

S. Przbylski, Cache and Memory Hierarchy Design: A Performance- Directed Approach, Morgan Kaufman, San Mateo CA, 1990.

Digital Library

[23]

M. Segal, C. Korobkin, R. van Widenfelt, J. Foran, and P. Haeberli, "Fast Shadows and Lighting Effects Using Texture Mapping," Computer Graphics (Proc. Siggraph), .luly 1992, pp. 249-252.

Digital Library

[24]

M. Shantz, D. Krasnov, A. Kibkalo, A. Subbotin, F. Xie, and T. Park, "Building Online Virtual Worlds," Graphicon-96, July 1-5 1996, GRAFO Computer Graphics Society, State Education Center, Saint Petersburg, Russia.

[25]

A. Silberschatz, J. Peterson. P. Galvin, Operating System Concepts, Addison-Wesley, Reading MA, 1991.

Digital Library

[26]

J. Torborg and J. Kajiya, "Talisman: Commodity Realtime 3D Graphics for the PC," Computer Graphics (Proc. Siggraph), August 1996, pp. 353-363.

Digital Library

[27]

Doug Voorhies, Nvidia Corporation, personal communication 1997.

[28]

A. Watt and M. Watt, Advanced Animation and Rendering Techniques." Theory, and Practice, Addison-Wesley, Reading MA, 1992.

[29]

T ~ Whitted, "An Improved Illumination Model for Shaded Display," Communications of the ACM, Vol. 23, No. 6, June 1980.

Digital Library

[30]

S. Winner, M. Kelley, B. Pease, B. Rivard, and A. Yen, "Hardware Accelerated Rendering of Antialiasing Using a Modified A-buffer Algorithm," Computer Graphics (Proc. Siggraph), August 1997, pp. 307- 316.

Digital Library

[31]

L. Williams, "Pyramidal Parametrics," Computer Graphics (Proc. Siggraph), July 1983, pp. 1-11.

Digital Library

Cited By

Domanski LSun CLagerstrom RWang DBischof LPayne MVallotton P(2011)High-Throughput Detection of Linear Features: Selected Applications in Biological ImagingMedical Image Processing10.1007/978-1-4419-9779-1_8(167-191)Online publication date: 15-Jun-2011
https://doi.org/10.1007/978-1-4419-9779-1_8
Silpa BPatney AKrishna TPanda PVisweswaran GNassif SRoychowdhury J(2008)Texture filter memoryProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509581(559-564)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509581
Luo HChen GLiu FLi PDing CShen XJacob B(2018)Footprint modeling of cache associativity and granularityProceedings of the International Symposium on Memory Systems10.1145/3240302.3240419(232-242)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3240302.3240419
Show More Cited By

Index Terms

Multi-level texture caching for 3D graphics hardware
1. Computing methodologies
  1. Artificial intelligence
    1. Computer vision
      1. Image and video acquisition
        3D imaging
  2. Computer graphics
    1. Animation
    2. Graphics systems and interfaces

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 26, Issue 3

Special Issue: Proceedings of the 25th annual international symposium on Computer architecture (ISCA '98)

June 1998

379 pages

ISSN:0163-5964

DOI:10.1145/279361

Chairmen:
Mateo Valero
Univ. Politecnica de Catalunya, Barcelona, Spain
,
Gurindar S. Sohi
Univ. of Wisconsin-Madison, Madison
,
Editor:
Doug DeGroot

Issue’s Table of Contents

ISCA '98: Proceedings of the 25th annual international symposium on Computer architecture
April 1998
402 pages
ISBN:0818684917
Chairmen:
Mateo Valero
Univ. Politecnica de Catalunya
,
Gurindar S. Sohi
Univ. of Wisconsin-Madison, Madison
,
Editor:
Doug DeGroot

Copyright © 1998 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 April 1998

Published in SIGARCH Volume 26, Issue 3

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Cited By

Domanski LSun CLagerstrom RWang DBischof LPayne MVallotton P(2011)High-Throughput Detection of Linear Features: Selected Applications in Biological ImagingMedical Image Processing10.1007/978-1-4419-9779-1_8(167-191)Online publication date: 15-Jun-2011
https://doi.org/10.1007/978-1-4419-9779-1_8
Silpa BPatney AKrishna TPanda PVisweswaran GNassif SRoychowdhury J(2008)Texture filter memoryProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509581(559-564)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509581
Luo HChen GLiu FLi PDing CShen XJacob B(2018)Footprint modeling of cache associativity and granularityProceedings of the International Symposium on Memory Systems10.1145/3240302.3240419(232-242)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1145/3240302.3240419
Kim YJo JJang HRhu MKim HKim JHunter HMoreno JEmer JSanchez D(2017)GPUpdProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123968(574-586)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123968
Rai SChaudhuri M(2016)Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous ProcessorsProceedings of the 2016 International Conference on Supercomputing10.1145/2925426.2926266(1-14)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1145/2925426.2926266
Chen YLiu YMacii E(2013)Dual-addressing memory architecture for two-dimensional memory access patternsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485308(71-76)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485308
Gaur JSrinivasan RSubramoney SChaudhuri MFarrens MKozyrakis C(2013)Efficient management of last-level caches in graphics processors for 3D scene rendering workloadsProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2540708.2540742(395-407)Online publication date: 7-Dec-2013
https://dl.acm.org/doi/10.1145/2540708.2540742
Euh JChittamuru JBurleson W(2005)Power-Aware 3D Computer Graphics RenderingJournal of VLSI Signal Processing Systems10.1023/B:VLSI.0000047269.03965.e939:1-2(15-33)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1023/B%3AVLSI.0000047269.03965.e9
Zhang ZZhu ZZhang X(2004)Design and Optimization of Large Size and Low Overhead Off-Chip CachesIEEE Transactions on Computers10.1109/TC.2004.2753:7(843-855)Online publication date: 1-Jul-2004
https://dl.acm.org/doi/10.1109/TC.2004.27
Chang FFarkas KRanganathan P(2002)Energy-driven statistical samplingProceedings of the 2nd international conference on Power-aware computer systems10.5555/1766991.1767002(110-129)Online publication date: 2-Feb-2002
https://dl.acm.org/doi/10.5555/1766991.1767002
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