Article

A pipelined configurable gate array for embedded processors

Authors:

Fabio CampiAuthors Info & Claims

FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

Pages 21 - 30

https://doi.org/10.1145/611817.611822

Published: 23 February 2003 Publication History

Abstract

In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit explicitly designed to implement additional reconfigurable pipelined datapaths, suitable for the design of reconfigurable processors. A VLIW reconfigurable processor has been implemented on silicon in a standard 0.18 μ m CMOS technology to prove the effectiveness of the proposed unit. Testing on a signal processing algorithms benchmark showed speedups from 4.3x to 13.5x and energy consumption reduction up to 92%.

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Cited By

Chevobbe SGuyetant S(2009)Reducing reconfiguration overheads in heterogeneous multicore RSoCs with predictive configuration managementInternational Journal of Reconfigurable Computing10.1155/2009/3901672009(4-4)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1155/2009/390167
Lodi ACappelli ABocchi MMucci CInnocenti MDe Bartolomeis CCiccarelli LGiansante RDeledda ACampi FToma MGuerrieri R(2006)XiSystem: a XiRisc-based SoC with reconfigurable IO moduleIEEE Journal of Solid-State Circuits10.1109/JSSC.2005.85931941:1(85-96)Online publication date: Jan-2006
https://doi.org/10.1109/JSSC.2005.859319
Bocchi MDominicis MMucci CDeledda ACampi FLodi AToma MGuerrieri R(2006)Design and implementation of a reconfigurable heterogeneous multiprocessor SoCIEEE Custom Integrated Circuits Conference 200610.1109/CICC.2006.320984(93-96)Online publication date: Sep-2006
https://doi.org/10.1109/CICC.2006.320984
Show More Cited By

Index Terms

A pipelined configurable gate array for embedded processors
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
      1. Microcomputers
2. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

cover image ACM Conferences

FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

February 2003

256 pages

ISBN:158113651X

DOI:10.1145/611817

General Chair:
Steve Trimberger
Xilinx
,
Program Chair:
Russ Tessier
University of Massachusetts - Amherst

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 23 February 2003

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FPGA03

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FPGA03: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2003

February 23 - 25, 2003

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Chevobbe SGuyetant S(2009)Reducing reconfiguration overheads in heterogeneous multicore RSoCs with predictive configuration managementInternational Journal of Reconfigurable Computing10.1155/2009/3901672009(4-4)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1155/2009/390167
Lodi ACappelli ABocchi MMucci CInnocenti MDe Bartolomeis CCiccarelli LGiansante RDeledda ACampi FToma MGuerrieri R(2006)XiSystem: a XiRisc-based SoC with reconfigurable IO moduleIEEE Journal of Solid-State Circuits10.1109/JSSC.2005.85931941:1(85-96)Online publication date: Jan-2006
https://doi.org/10.1109/JSSC.2005.859319
Bocchi MDominicis MMucci CDeledda ACampi FLodi AToma MGuerrieri R(2006)Design and implementation of a reconfigurable heterogeneous multiprocessor SoCIEEE Custom Integrated Circuits Conference 200610.1109/CICC.2006.320984(93-96)Online publication date: Sep-2006
https://doi.org/10.1109/CICC.2006.320984
Yiannacouras PRose JSteffan JConte TFaraboschi PMangione-Smith BNajjar W(2005)The microarchitecture of FPGA-based soft processorsProceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1086297.1086325(202-212)Online publication date: 24-Sep-2005
https://dl.acm.org/doi/10.1145/1086297.1086325
Lodi ACiccarelli LGiansante RSchmit HWilton S(2005)Combining low-leakage techniques for FPGA routing designProceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays10.1145/1046192.1046219(208-214)Online publication date: 20-Feb-2005
https://dl.acm.org/doi/10.1145/1046192.1046219
Mucci CCampi FDeledda AFazzi AFerri MBocchi M(2005)A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor ArchitectureProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 0410.1109/IPDPS.2005.14Online publication date: 4-Apr-2005
https://dl.acm.org/doi/10.1109/IPDPS.2005.14
Bilavarn SDebes EVandergheynst PDiguet J(2005)Processor Enhancements for Media Streaming ApplicationsJournal of VLSI Signal Processing Systems10.1007/s11265-005-6652-541:2(225-234)Online publication date: 1-Sep-2005
https://dl.acm.org/doi/10.1007/s11265-005-6652-5
Lodi AGiansante RChiesa CCiccarelli LCampi FToma M(2004)Compact Buffered Routing ArchitectureField Programmable Logic and Application10.1007/978-3-540-30117-2_20(179-188)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30117-2_20

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