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Memory aware compilation through accurate timing extraction

Authors:

Alex NicolauAuthors Info & Claims

DAC '00: Proceedings of the 37th Annual Design Automation Conference

Pages 316 - 321

https://doi.org/10.1145/337292.337428

Published: 01 June 2000 Publication History

Abstract

Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this bottleneck. However, such features can not be efficiently exploited in processor-based embedded systems without memory-aware compiler support. We describe a memory-aware compiler approach that exploits such efficient memory access modes by extracting accurate timing information, allowing the compiler's scheduler to perform global code reordering to better hide the latency of memory operations. Our memory-aware compiler scheduled several benchmarks on the TI C6201 processor architecture interfaced with a 2-bank synchronous DRAM and generated average improvements of 24% over the best possible schedule using a traditional (memory-transparent) optimizing compiler, demonstrating the utility of our memory-aware compilation approach.

References

[1]

HotChips conference,' 97 - '99.]]

[2]

E Chou, R. Ortega, and G. Borriello. Interface co-synthesis techniques for embedded systems. In ICCAD, 1995.]]

Digital Library

[3]

K.-S. Chung, R. Gupta, and C. L. Liu. Interface co-synthesis techniques for embedded systems. In ICCAD, 1996.]]

[4]

G.H. et al. ISDL: An instruction set description language for retargetability. In Proc. DAC, 1997.]]

Digital Library

[5]

M. Freericks. The nML machine description formalism. Technical Report TR SM-IMP/DIST/08, TU Berlin CS Dept., 1993.]]

[6]

E Grun, N. Dutt, and A. Nicolau. Extracting accurate timing information to support memory-aware compilation. Technical report, University of California, Irvine, 1999.]]

[7]

E Grun, A. Halambi, N. Dutt, and A. Nicolau. RTGEN: An algorithm for automatic generation of reservation tables from architectural descriptions. In ISSS, San Jose, CA, 1999.]]

Digital Library

[8]

J. Gyllenhaal. A machine description language for compilation. Master's thesis, Dept. of EE, UIUC,IL., 1994.]]

[9]

A. Halambi, E Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau. EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In Proc. DATE, Mar. 1999.]]

Digital Library

[10]

J. Hennessy and D. Patterson. Computer Architecture: A quantitative approach. Morgan Kaufmann Publishers Inc, San Mateo, CA, 1990.]]

Digital Library

[11]

IBM Microelectronics, Data Sheets for Synchronous DRAM IBM0316409C. www.chips.ibm.com/products/memory/O8J3348/.]]

[12]

A. Khare, E R. Panda, N. D. Dutt, and A. Nicolau. High level synthesis with synchronous and rambus drams. In SASIMI, Japan, 1998.]]

[13]

A. Khare, N. Savoiu, A. Halambi, E Grun, N. Dutt, and A. Nicolau. V-SAT: A visual specification and analysis tool for system-on-chip exploration. In Proc. EUROMICRO, 1999.]]

[14]

R. Leupers and E Marwedel. Retargetable code generation based on structural processor descriptions. Design Automation for Embedded Systems, 3(1), 1998.]]

[15]

T. Ly, D. Knapp, R. Miller, and D. MacMillen. Scheduling using behavioral templates. In DAC, San Francisco, 1995.]]

Digital Library

[16]

A. Nicolau and S. Novack. Trailblazing: A hierarchical approach to percolation scheduling. In ICPP, St. Charles, IL, 1993.]]

Digital Library

[17]

E R. Panda, N. D. Dutt, and A. Nicolau. Exploiting off-chip memory access modes in high-level synthesis. In IEEE Transactions on CAD, Feb. 1998.]]

Digital Library

[18]

B. Prince. High Performance Memories, New Architecture DRAMs and SRAMs evolution and function. Wiley, West Sussex, 1996.]]

[19]

S. Przybylski. Sorting out the new DRAMs. InHot Chips Tutorial, Stanford, CA, 1997.]]

[20]

Texas Instruments. TMS320C6201 CPU and Instruction Set Reference Guide.]]

[21]

Trimaran Release: http://www.trimaran.org. The MDES User Manual, 1997.]]

[22]

S. Wuytack, E Catthoor, G. de Jong, B. Lin, and H. D. Man. Flow graph balancing for minimizing the required memory bandwith. In ISSS, La Jolla, CA, 1996.]]

Digital Library

Cited By

Youn JCho D(2017)Improving memory system performance for multimedia applicationsMultimedia Tools and Applications10.1007/s11042-015-2807-y76:4(5951-5963)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1007/s11042-015-2807-y
Shrivastava ACai J(2017)Hardware-Aware CompilationHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_26(795-827)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_26
Jalan RKejariwal A(2012)Trin-Trin: Who’s Calling? A Pin-Based Dynamic Call Graph Extraction FrameworkInternational Journal of Parallel Programming10.1007/s10766-012-0193-x40:4(410-442)Online publication date: 12-May-2012
https://doi.org/10.1007/s10766-012-0193-x
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Published In

cover image ACM Conferences

DAC '00: Proceedings of the 37th Annual Design Automation Conference

June 2000

819 pages

ISBN:1581131879

DOI:10.1145/337292

Chairman:
Giovanni De Micheli
Stanford Univ., Stanford, CA

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 2000

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Cited By

Youn JCho D(2017)Improving memory system performance for multimedia applicationsMultimedia Tools and Applications10.1007/s11042-015-2807-y76:4(5951-5963)Online publication date: 1-Feb-2017
Shrivastava ACai J(2017)Hardware-Aware CompilationHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_26(795-827)Online publication date: 27-Sep-2017
Jalan RKejariwal A(2012)Trin-Trin: Who’s Calling? A Pin-Based Dynamic Call Graph Extraction FrameworkInternational Journal of Parallel Programming10.1007/s10766-012-0193-x40:4(410-442)Online publication date: 12-May-2012
Qin WMalik S(2010)Architecture Description Languages for Retargetable CompilationThe Compiler Design Handbook10.1201/9781420040579.ch14Online publication date: 7-Mar-2010
Malik SQin W(2009)Architecture Description Languages for Retargetable CompilationThe Compiler Design Handbook10.1201/9781420043839.ch16(16-1-16-27)Online publication date: 7-Dec-2009
Mi WFeng XJia YChen LXue J(2009)PARBLO: Page-Allocation-Based DRAM Row Buffer Locality OptimizationJournal of Computer Science and Technology10.1007/s11390-009-9297-124:6(1086-1097)Online publication date: 6-Nov-2009
Stitt GChaudhari GCoole JGebotys CMartin G(2008)Traversal cachesProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450150(61-66)Online publication date: 19-Oct-2008
Mishra PDutt N(2008)Processor Description LanguagesundefinedOnline publication date: 29-May-2008
Givargis T(2006)Zero cost indexing for improved processor cache performanceACM Transactions on Design Automation of Electronic Systems10.1145/1124713.112471511:1(3-25)Online publication date: 1-Jan-2006
Choi YKim THan H(2006)Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.83772124:2(278-287)Online publication date: 1-Nov-2006
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