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VLSI Circuits 2016: Honolulu, HI, USA
- 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016. IEEE 2016, ISBN 978-1-5090-0635-9
- Jeffrey C. Gealow, Masato Motomura
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Foreword. 1-2 - Olivier Temam:
Enabling future progress in machine-learning. 1-3 - Tetsuo Nomoto, Yusuke Oike, Hayato Wakabayashi:
Accelerating the Sensing world through imaging evolution. 1-4 - Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang:
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications. 1-2 - Makoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii:
A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time. 1-2 - Yukihide Tsuji
A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond. 1-2 - Janakiraman Viraraghavan
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. 1-2 - Koji Obata, Kazuo Matsukawa, Takuji Miki, Yusuke Tsukamoto, Koji Sushihara:
A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect. 1-2 - Yi Zhang, Chia-Hung Chen, Tao He, Gabor C. Temes:
A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator. 1-2 - Arindam Sanyal, Nan Sun:
A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration. 1-2 - Ankesh Jain
A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback. 1-2 - Seyed Mohammad Ali Zeinolabedin
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS. 1-2 - Zhewei Jiang, Joao Pedro Cerqueira, Seongjong Kim, Qi Wang, Mingoo Seok:
1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision. 1-2 - Jong Seok Park, Taiyun Chi, Amy Su, Chengjie Zhu, Jung Hoon Sung, Hee Cheol Cho, Mark P. Styczynski, Hua Wang
A high-density CMOS multi-modality joint sensor/stimulator array with 1024 pixels for holistic real-time cellular characterization. 1-2 - Chao Chen, Zhao Chen, Deep Bera, Shreyas B. Raghunathan, Maysam Shabanimotlagh, Emile Noothout, Zu-yao Chang, Jacco Ponte, Christian Prins, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs:
A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography. 1-2 - Parag Upadhyaya, Ade Bekele, Didem Turkur Melek, Haibing Zhao, Jay Im, Junho Cho, Kee Hian Tan, Scott McLeod, Stanley Chen, Wenfeng Zhang, Yohan Frans, Ken Chang:
A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology. 1-2 - Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka:
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. 1-2 - Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim:
A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. 1-2 - Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang:
A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. 1-2 - Xun Liu, Cheng Huang
A 50MHz 5V 3W 90% efficiency 3-level buck converter with real-time calibration and wide output range for fast-DVS in 65nm CMOS. 1-2 - Wen-Hau Yang, Chiun-He Lin, Ke-Horng Chen
95% light-load efficiency single-inductor dual-output DC-DC buck converter with synthesized waveform control technique for USB type-C. 1-2 - Se-un Shin, Min-Yong Jung, Kiduk Kim, Sang-Hui Park, Yeunhee Huh, Changsik Shin, Se-Hong Park
A reconfigurable SIMO system with 10-output dual-bus DC-DC converter using the load balancing function in group allocator for diversified load condition. 1-2 - Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Diego Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, José Pineda de Gyvez, Kofi A. A. Makinwa:
A microcontroller with 96% power-conversion efficiency using stacked voltage domains. 1-2 - Milovan Blagojevic, Martin Cochet, Ben Keller, Philippe Flatresse, Andrei Vladimirescu, Borivoje Nikolic
A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI. 1-2 - Feng-Wei Kuo, Sandro Binsfeld Ferreira
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter. 1-2 - Wootaek Lim, Tae-Kwang Jang
A 380pW dual mode optical wake-up receiver with ambient noise cancellation. 1-2 - Guerric de Streel, François Stas, Thibaut Gurne, François Durant
SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape. 1-2 - Seong Joong Kim, Chang Soon Park, Youngkyu Kim, Seok-Ju Yun, Young-Jun Hong, Sang-Gug Lee:
A 2.4GHz ternary sequence spread spectrum OOK transceiver with harmonic spur suppression and dual-mode detection architecture for ULP wearable devices. 1-2 - Yosuke Ogasawara, Hiroki Sakurai, Ryuichi Fujimoto, Kenichi Sami:
An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs. 1-2 - Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James W. Tschanz, Vivek De:
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. 1-2 - Patrick R. Gill, Thomas Vogelsang
Lensless Smart Sensors: Optical and thermal sensing for the Internet of Things. 1-2 - Yasuo Terasawa, Kenzo Shodo, Koji Osawa, Jun Ohta
Features of retinal prosthesis using suprachoroidal transretinal stimulation from an electrical circuit perspective. 1-2 - Ajit Sharma, Seung Bae Lee, Arup Polley, Sriram Narayanan, Wen Li, Terry Sculley, Srinath Ramaswamy:
Multi-modal smart bio-sensing SoC platform with >80dB SNR 35µA PPG RX chain. 1-2 - Takashi Shimizu, Yasumoto Tomita, Hidetoshi Matsumura, Masahiko Sugimura, Hironobu Yamasaki, David Thach, Takashi Miyoshi, Takayuki Baba, Yasuhiro Watanabe, Atsushi Ike:
An FPGA-accelerated partial image matching engine for massive media data searching systems. 1-2 - Xiao Wu, Yao Shi, Supreet Jeloka, Kaiyuan Yang
A 66pW discontinuous switch-capacitor energy harvester for self-sustaining sensor applications. 1-2 - Cheng Huang, Toru Kawajiri, Hiroki Ishikuro:
A wireless power transfer system with enhanced response and efficiency by fully-integrated fast-tracking wireless constant-idle-time control for implants. 1-2 - Chul Kim, Jiwoong Park, Abraham Akinin, Sohmyung Ha
A fully integrated 144 MHz wireless-power-receiver-on-chip with an adaptive buck-boost regulating rectifier and low-loss H-Tree signal distribution. 1-2 - Saleh Heidary Shalmany, Dieter Draxelmayr, Kofi A. A. Makinwa:
A ± 36A integrated current-sensing system with 0.3% gain error and 400µA offset from -55°C to +85°C. 1-2 - Qing Dong, Kaiyuan Yang
A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems. 1-2 - Alexander Tessarolo:
Motor Control used to be boring. 1-2 - Shinji Ujita, Yusuke Kinoshita, Hidekazu Umeda, Tatsuo Morita, Kazuhiro Kaibara, Satoshi Tamura, Masahiro Ishida, Tetsuzo Ueda
A fully integrated GaN-based power IC including gate drivers for high-efficiency DC-DC Converters. 1-2 - Ruida Yun, James Sun, Eric Gaalaas, Baoxing Chen
A transformer-based digital isolator with 20kVPK surge capability and > 200kV/µS Common Mode Transient Immunity. 1-2 - Alessandro Moscatelli:
Innovative system on chip platform for Smart Grids and internet of energy applications. 1-2 - Sameet Ramakrishnan, Lucas Calderin, Antonio Puglielli, Elad Alon, Ali M. Niknejad, Borivoje Nikolic
A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage. 1-2 - Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan
Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers. 1-2 - Yang Xu, Peter R. Kinget
A chopping switched-capacitor RF receiver with integrated blocker detection, +31dBm OB-IIP3, and +15dBm OB-B1dB. 1-2 - Jianhong Xiao, Weinan Gao, Xiaojing Xu, Dave S.-H. Chang, Jiang Cao, Runhua Sun, Vijay Periasamy, Ning-Yi Wang, Xi Chen, Greg Unruh, Takayuki Hayashi, Tai-Hong Chih, Lakshminarasimhan Krishnan, Kuo-Ken Huang, Sunny Raj Dommaraju, Guowen Wei, Bo Shen, Ardie G. Venes, Dongsoo Koh, James Y. C. Chang:
A 180 mW multistandard TV tuner in 28 nm CMOS. 1-2 - Sangheon Lee, Jeonghwan Song, Changhyuk Seong, Jiyong Woo, Jong-Moon Choi, Soon-Chan Kwon, Ho-Joon Kim, Hyun-Suk Kang, Soo Gil Kim, Hoe Gwon Jung, Kee-Won Kwon, Hyunsang Hwang:
Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier. 1-2 - Tatsuya Onuki, Wataru Uesugi, Hikaru Tamura, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew, Chen Bin Lin, J. Y. Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki:
Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. 1-2 - Atsuro Kobayashi, Tsukasa Tokutomi, Ken Takeuchi:
Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers. 1-2 - Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang:
A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. 1-2 - Yang Xu, Spencer Leuenberger, Praveen Kumar Venkatachala, Un-Ku Moon:
A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS. 1-2 - Tilo Meister
3.5mW 1MHz AM detector and digitally-controlled tuner in a-IGZO TFT for wireless communications in a fully integrated flexible system for audio bag. 1-2 - Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey A. Fredenburg, Michael P. Flynn:
A 16-channel noise-shaping machine learning analog-digital interface. 1-2 - Yunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, Jaeha Kim:
A field-programmable mixed-signal IC with time-domain configurable analog blocks. 1-2 - Brent Bohnenstiehl, Aaron Stillmaker
A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array. 1-2 - Rossella Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, Daniel Noblet, Damien Croain, Fabien Giner, Sylvie Naudet, P. Mergault, S. Ibars, A. Villaret, Maryline Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud:
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications. 1-2 - Azeez Bhavnagarwala, Imran Iqbal, An Nguyen, David Ondricek, Vikas Chandra, Robert C. Aitken:
A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um2 6T bitcell in a 16nm FinFET CMOS process. 1-2 - Amit Agarwal, Steven Hsu, Mark A. Anders, Sanu Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir Satpathy, Ram Krishnamurthy:
A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS. 1-2 - Seung Chul Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, Joseph Wang, G. Nallapati, Mustafa Badaroglu, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap:
Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. 1-2 - Jae-Won Nam
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. 1-2 - Yuan-Ching Lien:
A 14.6mW 12b 800MS/s 4×time-interleaved pipelined SAR ADC achieving 60.8dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibration. 1-2 - Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung
An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC. 1-2 - Sung-En Hsieh, Chih-Cheng Hsieh:
A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC. 1-2 - A. K. M. Delwar Hossain, Aurangozeb
A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS. 1-2 - Bharath Raghavan, Aida Varzaghani, Lakshmi P. Rao
A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS. 1-2 - Ryan Boesch, Kevin Zheng, Boris Murmann
A 0.003 mm2 5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE. 1-2 - Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, Sheau Jiung Lee, Mau-Chung Frank Chang
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. 1-2 - Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Young Jae Jang, Young-Chul Cho, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. 1-2 - Bert Moons, Marian Verhelst
A 0.3-2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets. 1-2 - Phil Knag, Chester Liu, Zhengya Zhang
A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS. 1-2 - Richard Dorrance
A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT. 1-2 - Amr Suleiman, Zhengdong Zhang, Vivienne Sze:
A 58.6mW real-time programmable object detector with multi-scale multi-object support using deformable parts model on 1920×1080 video at 30fps. 1-2 - Minki Cho, Carlos Tokunaga
Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. 1-2 - Jian Zhao, Xi Wang, Yang Zhao, Guo Ming Xia, An Ping Qiu, Yan Su, Yong Ping Xu:
A 0.23 µg bias instability and 1.6 µg/Hz1/2 resolution silicon oscillating accelerometer with build-in Σ-Δ frequency-to-digital converter. 1-2 - Bahman Yousefzadeh, Saleh Heidary Shalmany, Kofi A. A. Makinwa:
A BJT-based temperature-to-digital converter with ±60mK (3σ) inaccuracy from -70°C to 125°C in 160nm CMOS. 1-2 - Matthias Eberlein
A 28nm CMOS ultra-compact thermal sensor in current-mode technique. 1-2 - Hesham Omran
A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operation. 1-2 - Yan Hong, Yong Wang, Wang Ling Goh, Yuan Gao
A 9.84-73.2 nJ, 0.048 mm2 time-domain impedance sensor that provides values of resistance and capacitance. 1-2 - Benwei Xu, Yuan Zhou, Yun Chiu
A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS. 1-2 - Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu:
A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS. 1-2 - Ahmed M. A. Ali
A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither. 1-2 - Vishnu Ravinuthula, William Bright, Mark Weaver, Kenneth Maclean, Scott Kaylor, Sidharth Balasubramanian, Jesse Coulon, Robert Keller, Bao Nguyen, Ebenezer Dwobeng:
A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz. 1-2 - Mayank Raj, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET. 1-2 - Amit Jha
-197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS. 1-2 - Saman Saeedi, Azita Emami
A 10Gb/s, 342fJ/bit micro-ring modulator transmitter with switched-capacitor pre-emphasis and monolithic temperature sensor in 65nm CMOS. 1-2 - Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo, Tatemi Ido:
A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology. 1-2 - Yusuke Oike, Kentaro Akiyama, Luong D. Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito Sakano, Yoshiaki Kitano, Takuya Nakamura, Takayuki Toyama, Hayato Iwamoto, Takayuki Ezaki:
An 8.3M-pixel 480fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structure. 1-2 - Hidetake Sugo, Shunichi Wakashima, Rihito Kuroda
A dead-time free global shutter CMOS image sensor with in-pixel LOFIC and ADC using pixel-wis e connections. 1-2 - Suyao Ji, Jing Pu, ByongChan Lim, Mark Horowitz:
A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture. 1-2 - Sechang Oh
A 260µW infrared gesture recognition system-on-chip for smart devices. 1-2 - Alvin Li, Yue Chao, Xuan Chen, Liang Wu, Howard C. Luong
An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique. 1-2 - Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu:
An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. 1-2 - Long Kong, Behzad Razavi:
A 2.4-GHz 6.4-mW fractional-N inductorless RF synthesizer. 1-2 - Yongsun Lee, Heein Yoon, Mina Kim, Jaehyouk Choi
A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop. 1-2 - Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski
A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. 1-2 - Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy:
250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. 1-2 - Yiqun Zhang, Kaiyuan Yang
A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm. 1-2 - Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De:
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. 1-2 - Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector. 1-2 - Jintao Zhang, Zhuo Wang, Naveen Verma:
A machine-learning classifier implemented in a standard 6T SRAM array. 1-2 - Mahsa Shoaran
A 16-channel 1.1mm2 implantable seizure control SoC with sub-μW/channel consumption and closed-loop stimulation in 0.18µm CMOS. 1-2 - Xinyue Yuan
A microelectrode array with 8, 640 electrodes enabling simultaneous full-frame readout at 6.5 kfps and 112-channel switch-matrix readout at 20 kS/s. 1-2 - Xiong Zhou, Qiang Li, Soren Kilsgaard, Farshad Moradi
A wearable ear-EEG recording system based on dry-contact active electrodes. 1-2 - Gunpil Hwang, JongKwan Choi, Jaehyeok Yang, Sungmin Lim, Jae-Myoung Kim, MinGyu Choi, Dae-Shik Kim, Kiuk Gwak, Jinwoo Jeon, Hee Sup Shin, Il-Hwan Choi, Sol Park, Hyeon-Min Bae:
A 2.048 Mb/s full-duplex free-space optical transceiver IC for a real-time in vivo neurofeedback mouse experiment under social interaction. 1-2 - Seongjong Kim, Joao Pedro Cerqueira, Mingoo Seok:
A 450mV timing-margin-free waveform sorter based on body swapping error correction. 1-2
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