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2020 – today
- 2024
- [j77]Shanthi Pavan
, Saravana Manivannan
Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining. IEEE J. Solid State Circuits 59(1): 268-281 (2024) - [j76]Javad Gorji
On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1082-1092 (2024) - [c60]Shanthi Pavan:
Systematic Development of CMOS PTAT Circuits. ISCAS 2024: 1-5 - 2023
- [j75]Shanthi Pavan
Reciprocity and Inter-Reciprocity: A Tutorial - Part I: Linear Time-Invariant Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3413-3421 (2023) - [j74]Shanthi Pavan
Reciprocity and Inter-Reciprocity: A Tutorial - Part II: Linear Periodically Time-Varying Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3422-3435 (2023) - [j73]Chaitanya Kumar
Power-Noise Trade-Offs in Continuous-Time Pipelined ADCs and Active Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3832-3842 (2023) - [j72]Nishanth Basavaraj
Digital Reconstruction in Continuous-Time Pipelined Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5086-5097 (2023) - [c59]Alok Baluni, Shanthi Pavan:
A 13.5 mW Decimator for a 20 MHz bandwidth CTΔΣ Modulator using poly-phase decomposition techniques. ICECS 2023: 1-6 - [c58]Javad Gorji
Bandpass $\Delta \Sigma$ Modulators with FIR Feedback. ISCAS 2023: 1-5 - 2022
- [j71]Raviteja Theertham
Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs. IEEE J. Solid State Circuits 57(11): 3418-3428 (2022) - [j70]Shanthi Pavan
Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 530-540 (2022) - [j69]Saravana Manivannan
Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3102-3113 (2022) - [j68]Raviteja Theertham, Shanthi Pavan
Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 1991-1995 (2022) - [j67]Shanthi Pavan
Systematic Development of CMOS Fixed-Transconductance Bias Circuits. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2394-2397 (2022) - [j66]Nishanth Basavaraj
Simplified Simulation and Measurement of the Signal Transfer Function of a Continuous-Time Pipelined Analog-to-Digital Converter. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 3993-3997 (2022) - [c57]Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun:
A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. CICC 2022: 1-2 - [c56]Chaitanya Kumar
Analysis of Flash ADC Loading on the Performance of a Continuous-Time Pipelined ADC. ISCAS 2022: 2792-2796 - 2021
- [j65]Alok Baluni
Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback. IEEE J. Solid State Circuits 56(3): 729-738 (2021) - [j64]Shanthi Pavan
Continuous-Time Incremental Delta-Sigma Modulators With FIR Feedback. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3222-3231 (2021) - [j63]Shanthi Pavan
Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 810-815 (2021) - [c55]Udita Mukherjee, Tanmay Halder
A 28.5µW All-Analog Voice-Activity Detector. ISCAS 2021: 1-5 - 2020
- [j62]Raviteja Theertham
Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density. IEEE J. Solid State Circuits 55(9): 2429-2442 (2020) - [j61]Sujith Billa, Suhas Dixit, Shanthi Pavan
Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator. IEEE J. Solid State Circuits 55(10): 2649-2659 (2020) - [j60]Saravana Manivannan
Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering. IEEE Trans. Circuits Syst. 67-I(11): 3778-3789 (2020) - [c54]Alok Baluni, Shanthi Pavan:
A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC. CICC 2020: 1-4 - [c53]Raviteja Theertham, Shanthi Pavan:
Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. ISCAS 2020: 1 - [c52]Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. ISSCC 2020: 260-262
2010 – 2019
- 2019
- [j59]Sundeep Javvaji
Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting. IEEE J. Solid State Circuits 54(9): 2590-2600 (2019) - [j58]Shanthi Pavan
An Alternative Approach to Bode's Noise Theorem. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 738-742 (2019) - [j57]Raviteja Theertham, Shanthi Pavan
Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2831-2842 (2019) - [j56]Kishalay Datta
Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 3227-3237 (2019) - [j55]Shanthi Pavan
Improved Offline Calibration of DAC Mismatch Errors in Delta-Sigma Data Converters. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1618-1622 (2019) - [c51]Sujith Billa, Suhas Dixit, Shanthi Pavan:
A 265μW Continuous-Time 1-2 MASH ADC Achieving 100.6 dB SNDR in a 24 kHz Bandwidth. A-SSCC 2019: 123-124 - [c50]Saravana Manivannan, Shanthi Pavan:
Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities. ISCAS 2019: 1-5 - [c49]Shanthi Pavan:
Simplified Analysis of Total Integrated Noise in Passive Switched-Capacitor and N-Path Filters. ISCAS 2019: 1-5 - [c48]Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan:
A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth. VLSI Circuits 2019: 226- - 2018
- [j54]Ankesh Jain
Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 434-443 (2018) - [j53]Shanthi Pavan
Improved Chopping in Continuous-Time Delta-Sigma Converters Using FIR Feedback and N-Path Techniques. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 552-556 (2018) - [j52]Shanthi Pavan
Analysis of the Effect of Source Capacitance and Inductance on $N$ -Path Mixers and Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1469-1480 (2018) - [j51]Saravana Manivannan
Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3207-3215 (2018) - [j50]Shanthi Pavan
Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3267-3278 (2018) - [c47]Saravana Manivannan, Shanthi Pavan:
A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR. CICC 2018: 1-4 - [c46]Shanthi Pavan:
Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters. CICC 2018: 1-8 - [c45]Shanthi Pavan:
Practical design and simulation techniques for continuous-time ΔΣ converters. CICC 2018: 1-81 - [c44]Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan:
Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting. ESSCIRC 2018: 42-45 - [c43]Shanthi Pavan, Siddharth Baskaran:
What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator? ISCAS 2018: 5- - 2017
- [j49]Neha Sinha
Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components. IEEE J. Solid State Circuits 52(8): 2009-2025 (2017) - [j48]Sujith Billa, Amrith Sukumaran
Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping. IEEE J. Solid State Circuits 52(9): 2350-2361 (2017) - [j47]Hajime Shibata
A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD. IEEE J. Solid State Circuits 52(12): 3219-3234 (2017) - [j46]Shanthi Pavan
Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 1953-1965 (2017) - [j45]Shanthi Pavan
Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2714-2725 (2017) - [c42]Shanthi Pavan:
On linear periodically time varying (LPTV) systems with modulated inputs, and their application to smoothing filters. ISCAS 2017: 1-4 - 2016
- [j44]Amrith Sukumaran
Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs. IEEE J. Solid State Circuits 51(7): 1619-1629 (2016) - [c41]Shanthi Pavan:
Continuous-time ΔΣ modulators with dual switched capacitor resistor DACs. ISCAS 2016: 69-72 - [c40]Sujith Billa, Amrith Sukumaran
15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts. ISSCC 2016: 276-277 - [c39]Ankesh Jain
A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback. VLSI Circuits 2016: 1-2 - [c38]Shanthi Pavan, Nagendra Krishnapura:
Demystifying Time Varying Circuits and Systems. VLSID 2016: 17-18 - [c37]Kamlesh Singh
A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition. VLSID 2016: 230-235 - 2015
- [j43]José M. de la Rosa
Guest Editorial: Next-Generation Delta-Sigma Converters. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(4): 481-483 (2015) - [j42]José M. de la Rosa
Next-Generation Delta-Sigma Converters: Trends and Perspectives. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(4): 484-499 (2015) - [j41]Shanthi Pavan:
Outgoing Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2793-2794 (2015) - [c36]Amrith Sukumaran
A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC. ESSCIRC 2015: 217-220 - [c35]Naga Rajesh, Shanthi Pavan:
Programmable analog pulse shaping for ultra-wideband applications. ISCAS 2015: 461-464 - [c34]Sandeep Krishnan, Shanthi Pavan:
A 10 Gbps eye opening monitor in 65nm CMOS. ISCAS 2015: 3028-3031 - 2014
- [j40]Naga Rajesh, Shanthi Pavan:
Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming. IEEE J. Solid State Circuits 49(8): 1800-1814 (2014) - [j39]Radha S. Rajan, Shanthi Pavan:
Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering. IEEE J. Solid State Circuits 49(10): 2187-2198 (2014) - [j38]Amrith Sukumaran
Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback. IEEE J. Solid State Circuits 49(11): 2515-2525 (2014) - [j37]Shanthi Pavan:
Incoming Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 1 (2014) - [j36]Yong Lian
Guest Editorial Special Section on the 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013). IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1301-1303 (2014) - [j35]Ankesh Jain
Characterization Techniques for High Speed Oversampled Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1313-1320 (2014) - [j34]Shanthi Pavan:
Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1629-1637 (2014) - [j33]Shanthi Pavan, Radha S. Rajan:
Simplified Analysis and Simulation of the STF, NTF, and Noise in Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs 61-II(9): 681-685 (2014) - [j32]Shanthi Pavan, Radha S. Rajan:
Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs. IEEE Trans. Circuits Syst. II Express Briefs 61-II(9): 686-690 (2014) - [c33]Shanthi Pavan:
Efficient estimation of noise and signal transfer functions of a continuous-time ΣΔ modulator. ISCAS 2014: 726-729 - [c32]Radha S. Rajan, Shanthi Pavan:
29.1 A 5mW CT ΔΣ ADC with embedded 2nd-order active filter and VGA achieving 82dB DR in 2MHz BW. ISSCC 2014: 478-479 - 2013
- [j31]Timir Nandi, Karthikeya Boominathan, Shanthi Pavan:
Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC. IEEE J. Solid State Circuits 48(8): 1795-1805 (2013) - [j30]Shanthi Pavan:
A Time-Domain Perspective of the Signal Transfer Function of a Continuous-Time ΔΣ Modulator. IEEE Trans. Circuits Syst. II Express Briefs 60-II(2): 81-85 (2013) - [j29]Shanthi Pavan, Wouter A. Serdijn, Henry Shu-Hung Chung, Ming-Der Shieh, Young Hwan Kim:
Guest Editorial Special Section on the 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012). IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5): 1101-1103 (2013) - [j28]Shanthi Pavan, John W. M. Rogers, Vikas Chandra:
Guest Editorial: Special Section on the 2012 IEEE Custom Integrated Circuits Conference (CICC 2012). IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 1977-1978 (2013) - [c31]Naga Rajesh, Shanthi Pavan:
A lumped component programmable delay element for Ultra-Wideband beamforming. CICC 2013: 1-4 - [c30]Ankesh Jain
Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface. ISCAS 2013: 1252-1255 - 2012
- [j27]Ankesh Jain
Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique. IEEE J. Solid State Circuits 47(7): 1615-1625 (2012) - [j26]Vikas Singh, Nagendra Krishnapura
A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay. IEEE J. Solid State Circuits 47(8): 1884-1895 (2012) - [j25]Pradeep Shettigar, Shanthi Pavan:
Design Techniques for Wideband Single-Bit Continuous-Time Delta Sigma Modulators With FIR Feedback DACs. IEEE J. Solid State Circuits 47(12): 2865-2879 (2012) - [j24]Chip-Hong Chang
Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011). IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1601-1603 (2012) - [j23]Radha S. Rajan, Shanthi Pavan:
Device Noise in Continuous-Time Oversampling Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1829-1840 (2012) - [c29]Timir Nandi, Karthikeya Boominathan, Shanthi Pavan:
A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC. CICC 2012: 1-4 - [c28]Radha S. Rajan, Shanthi Pavan:
Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs. ISCAS 2012: 524-527 - [c27]Pradeep Shettigar, Shanthi Pavan:
A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS. ISSCC 2012: 156-158 - [c26]Un-Ku Moon, Shanthi Pavan:
Little-known features of well-known creatures. ISSCC 2012: 511 - 2011
- [j22]Siva V. Thyagarajan, Shanthi Pavan, Prabu Sankar:
Active-RC Filters Using the Gm-Assisted OTA-RC Technique. IEEE J. Solid State Circuits 46(7): 1522-1533 (2011) - [j21]Shanthi Pavan:
Alias Rejection of Continuous-Time DeltaSigma Modulators With Switched-Capacitor Feedback DACs. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(2): 233-243 (2011) - [j20]Shanthi Pavan:
On Continuous-Time DeltaSigma Modulators With Return-to-Open DACs. IEEE Trans. Circuits Syst. II Express Briefs 58-II(5): 284-288 (2011) - [c25]Vikas Singh, Nagendra Krishnapura
A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. CICC 2011: 1-4 - [c24]Ankesh Jain
A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range. ESSCIRC 2011: 259-262 - [c23]Shanthi Pavan:
The inconvenient truth about alias rejection in continuous time ΔΣ converters. ISCAS 2011: 526-529 - 2010
- [j19]Shanthi Pavan, Prabu Sankar:
Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique. IEEE J. Solid State Circuits 45(7): 1365-1379 (2010) - [j18]Shanthi Pavan:
Systematic Design Centering of Continuous Time Oversampling Converters. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 158-162 (2010) - [j17]Shanthi Pavan:
Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 1925-1934 (2010) - [j16]Vikas Singh, Nagendra Krishnapura
Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 676-680 (2010) - [c22]Siva V. Thyagarajan, Shanthi Pavan, Prabu Sankar:
Low distortion active filters using the Gm-assisted OTA-RC technique. ESSCIRC 2010: 162-165 - [c21]Shanthi Pavan:
Understanding weak loop filter nonlinearities in continuous time ΔΣ converters. ISCAS 2010: 17-20
2000 – 2009
- 2009
- [j15]Tonse Laxminidhi, Venkata Prasadu, Shanthi Pavan:
Widely Programmable High-Frequency Active RC Filters in CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 327-336 (2009) - [c20]Shanthi Pavan, Prabu Sankar:
A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range. ESSCIRC 2009: 320-323 - [c19]Yogesh Darwhekar, Rakesh Kumar, Debapriya Sahu, Shanthi Pavan, Ashish Lachhwani, T. Krishnaswamy, Subhashish Mukherjee:
A Digitally Assisted Baseband Filter with 9MHz Bandwidth and 0.3 dB IQ Mismatch for a WLAN Receiver Chain. ISCAS 2009: 261-264 - [c18]Saurabh Saxena
Automatic Tuning of Time Constants in Single Bit Continuous-time Delta-sigma Modulators. ISCAS 2009: 2257-2260 - [c17]Nagendra Krishnapura, Shanthi Pavan:
Negative Feedback System and Circuit Design. VLSI Design 2009: 35-36 - 2008
- [j14]Shanthi Pavan, Nagendra Krishnapura
A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications. IEEE J. Solid State Circuits 43(2): 351-360 (2008) - [j13]Shanthi Pavan:
Power and Area-Efficient Adaptive Equalization at Microwave Frequencies. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1412-1420 (2008) - [j12]Shanthi Pavan:
Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs 55-II(11): 1119-1123 (2008) - [c16]Karthikeyan Reddy, Shanthi Pavan:
A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range. ESSCIRC 2008: 210-213 - [c15]Shanthi Pavan:
Power and area efficient high speed analog adaptive equalization. ISCAS 2008: 3126-3129 - [c14]Shanthi Pavan, Nagendra Krishnapura:
Oversampling Analog-to-Digital Converter Design. VLSI Design 2008: 7 - 2007
- [j11]Shanthi Pavan, Tonse Laxminidhi:
Accurate Characterization of Integrated Continuous-Time Filters. IEEE J. Solid State Circuits 42(8): 1758-1766 (2007) - [j10]Shanthi Pavan, Rajesh Tiruvuru:
Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(2): 401-410 (2007) - [j9]Shanthi Pavan, Nagendra Krishnapura
Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs 54-II(4): 308-312 (2007) - [j8]Tonse Laxminidhi, Shanthi Pavan:
Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(7): 1481-1488 (2007) - [j7]Karthikeyan Reddy, Shanthi Pavan:
Fundamental Limitations of Continuous-Time Delta-Sigma Modulators Due to Clock Jitter. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(10): 2184-2194 (2007) - [j6]Prabu Sankar, Shanthi Pavan:
Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs 54-II(12): 1125-1129 (2007) - [c13]Tonse Laxminidhi, Venkata Prasadu, Shanthi Pavan:
A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS. CICC 2007: 683-686 - [c12]Shanthi Pavan, Nagendra Krishnapura
A 90μW 15-bit ΔΣ ADC for digital audio. ESSCIRC 2007: 198-201 - [c11]Tonse Laxminidhi, Shanthi Pavan:
Design Centering High Frequency Integrated Continuous-Time Filters. ISCAS 2007: 1939-1942 - [c10]Shanthi Pavan:
Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive Equalization. ISCAS 2007: 3550-3553 - 2006
- [j5]Venkata Srinivas, Shanthi Pavan, Ashish Lachhwani, Naga Sasidhar:
A Distortion Compensating Flash Analog-to-Digital Conversion Technique. IEEE J. Solid State Circuits 41(9): 1959-1969 (2006) - [j4]Shanthi Pavan, Shankar Shivappa:
Nonidealities in traveling wave and transversal FIR filters operating at microwave frequencies. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(1): 177-192 (2006) - [c9]Shanthi Pavan, Tonse Laxminidhi:
A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters. CICC 2006: 77-80 - [c8]Murali Shanmugasundaram, Shanthi Pavan:
Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A. CICC 2006: 201-204 - [c7]Karthikeyan Reddy, Shanthi Pavan:
Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter. ISCAS 2006 - [c6]Rajesh Tiruvuru, Shanthi Pavan:
Transmission line based FIR structures for high speed adaptive equalization. ISCAS 2006 - [c5]Shanthi Pavan, Prakash Easwaran, C. Srinivasan:
System Aspects of Analog to Digital Converter Designs. VLSI Design 2006: 10 - 2005
- [c4]Shanthi Pavan, Shankar Shivappa:
Analysis of traveling wave and transversal analog adaptive equalizers. ISCAS (6) 2005: 5962-5965 - 2004
- [j3]Shanthi Pavan:
Continuous-time integrated FIR filters at microwave frequencies. IEEE Trans. Circuits Syst. II Express Briefs 51-II(1): 15-20 (2004) - [c3]Shanthi Pavan:
A fixed transconductance bias technique for CMOS analog integrated circuits. ISCAS (1) 2004: 661-664 - 2001
- [c2]Gennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan:
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. CICC 2001: 153-156 - 2000
- [j2]Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj:
Widely programmable high-frequency continuous-time filters in digital CMOS technology. IEEE J. Solid State Circuits 35(4): 503-511 (2000) - [j1]Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan:
A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. IEEE J. Solid State Circuits 35(12): 1760-1768 (2000)
1990 – 1999
- 1999
- [c1]Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj:
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes. ISCAS (6) 1999: 202-205
Coauthor Index
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Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 22:23 CEST by the dblp team
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