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2020 – today
- 2024
- [j19]Hyun-A. Ahn
, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications. IEEE J. Solid State Circuits 59(10): 3479-3487 (2024) - [c32]IkJoon Choi, Seunghwan Hong, Kihyun Kim, Jeongsik Hwang, Seunghan Woo, Young-Sang Kim, Cheongryong Cho, Eun-Young Lee, Hun-Jae Lee, Min-Su Jung, Hee-Yun Jung, Ju-Seong Hwang, Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee, Jong-Eun Lee, Jun-Hyung Kim, Young-Kwan Kim, Su-Jin Park, Byung-Kyu Ho, Byongwook Na, Hye-In Choi, Chung-Ki Lee, Soo-Jung Lee, Hyunsung Shin, Young-Kyu Lee, Jang-Woo Ryu, Sangwoong Shin, Sungchul Park, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, SangJoon Hwang:
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process. ISSCC 2024: 234-236 - 2023
- [c31]Hyun-A. Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun-Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-Young Oh:
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. A-SSCC 2023: 1-4 - 2021
- [j18]Chang-Kyo Lee
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. IEEE J. Solid State Circuits 56(1): 212-224 (2021) - [j17]Min-Kyun Chae, Hye-Jung Kwon, Seung-Jun Bae, Nam-Jong Kim, Hong-June Park
A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2409-2413 (2021) - [c30]Meng-Fan Chang, Ru Huang, Seung-Jun Bae:
Session 16 Overview: Computation in Memory Memory Subcommittee. ISSCC 2021: 244-245 - [c29]Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, Min-Su Ahn, Dongkeon Lee, Seung-Hyun Cho, Dong-Yeon Park, Young-Jae Park, Min-Soo Jang, Yong-Jun Kim, Jinyong Choi, Sung-Woo Yoon, Jae-Woo Jung, Jae-Koo Park, Jae-Woo Lee, Dae-Hyun Kwon, Hyung-Seok Cha, Si-Hyeong Cho, Seong-Hoon Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim, Byung-Cheol Kim, Young-Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chanyoung Kim, Byongwook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee:
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. ISSCC 2021: 346-348 - 2020
- [j16]Kyung-Soo Ha
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. IEEE J. Solid State Circuits 55(1): 157-166 (2020) - [c28]Hyung-Joon Chi, Chang-Kyo Lee, Junghwan Park, Jin-Seok Heo, Jaehoon Jung, Dongkeon Lee, Dae-Hyun Kim
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. ISSCC 2020: 382-384
2010 – 2019
- 2019
- [j15]Yohan Frans
Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 54(1): 3-5 (2019) - [j14]Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Min-Su Ahn, Yong-Hun Kim, Yong Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyung-Bae Park, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Yong-Jun Kim, Young-Hun Seo, Chang-Ho Shin, ChanYong Lee, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin:
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. IEEE J. Solid State Circuits 54(1): 197-209 (2019) - [c27]Xi Yang, Seung-Jun Bae, Hae-Seung Lee:
An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS. ESSCIRC 2019: 305-308 - [c26]Jin-Seok Heo, Kihan Kim, Dong-Hoon Lee, Chang-Kyo Lee, Daesik Moon, Kiho Kim, Jin-Hyeok Baek, Sung-Woo Yoon, Hui-Kap Yang, Kyungryun Kim, Youngjae Kim, Bokgue Park, Su-Jin Park, Joung-Wook Moon, Jae-Hyung Lee, Yun-Sik Park, Soobong Jang, Seok-Hun Hyun, Hyuck-Joon Kwon, Jung-Hwan Choi, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee:
A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration. VLSI Circuits 2019: 114- - 2018
- [j13]Il-Min Yi
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface. IEEE J. Solid State Circuits 53(1): 144-154 (2018) - [j12]Chang-Kyo Lee
Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. IEEE J. Solid State Circuits 53(10): 2906-2916 (2018) - [c25]Seung-Jun Bae, Wolfgang Spirkl, Leland Chang:
Session 12 overview: DRAM: Memory subcommittee. ISSCC 2018: 202-203 - [c24]Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, ChanYong Lee, YoungSeok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. ISSCC 2018: 204-206 - [c23]Jin-Hyeok Baek, Chang-Kyo Lee, Kiho Kim, Daesik Moon, Gil-Hoon Cha, Jin-Seok Heo, Min-Su Ahn, Dong-Ju Kim, Jae-Joon Song, Seokhong Kwon, Jongmin Kim, Kyung-Soo Kim, Jinoh Ahn, Jeong-Sik Nam, Byung-Cheol Kim, Jeong-Hyeon Cho, Jeonghoon Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Ilgweon Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang:
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. VLSI Circuits 2018: 147-148 - 2017
- [c22]Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae-Sung Kim, Hyunyoon Cho, Young Hoon Son, Seonghwan Kim, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, Seungseob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, Tae-Young Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Joon-Young Park, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang:
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. A-SSCC 2017: 153-156 - [c21]Takefumi Yoshikawa, Seung-Jun Bae, Leland Chang:
Session 23 overview: DRAM, MRAM & DRAM interfaces. ISSCC 2017: 386-387 - [c20]Chang-Kyo Lee, Yoon-Joo Eom, Jin-Hee Park, Junha Lee, Hye-Ran Kim, Kihan Kim, Young Choi, Ho-Jun Chang, Jonghyuk Kim, Jong-Min Bang, Seungjun Shin, Hanna Park, Su-Jin Park, Young-Ryeol Choi, Hoon Lee, Kyong-Ho Jeon, Jae-Young Lee, Hyo-Joo Ahn, Kyoung-Ho Kim, Jung-Sik Kim, Soobong Chang, Hyong-Ryol Hwang, Duyeul Kim, Yoon-Hwan Yoon, Seok-Hun Hyun, Joon-Young Park, Yoon-Gyu Song, Youn-Sik Park, Hyuck-Joon Kwon, Seung-Jun Bae, Tae-Young Oh, Indal Song, Yong-Cheol Bae, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin:
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme. ISSCC 2017: 390-391 - [c19]Hye-Jung Kwon, Eunsung Seo
23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices. ISSCC 2017: 394-395 - [c18]Il-Min Yi
23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS. ISSCC 2017: 400-401 - [c17]Yohan Frans, Ichiro Fujimori, Seung-Jun Bae, Samuel Palermo, Hideyuki Nosaka, Simone Erba:
F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond. ISSCC 2017: 512-514 - 2016
- [j11]Il-Min Yi
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 122-133 (2016) - [c16]Minhye Kim, Soochang Chae, Young-Ju Kim, Seung-Jun Bae, Lee-Sup Kim:
Crosstalk avoidance code for direct pass-through architecture. ISCAS 2016: 2475-2478 - [c15]Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim, Yong-Jun Kim, Ju-Hwan Kim, Won-Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung-Bum Ko, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin:
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. ISSCC 2016: 314-315 - [c14]Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Young Jae Jang, Young-Chul Cho, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. VLSI Circuits 2016: 1-2 - 2015
- [j10]Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Lee-Sup Kim:
A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2495-2503 (2015) - [c13]Chang-Kyo Lee, Min-Su Ahn, Daesik Moon, Kiho Kim, Yoon-Joo Eom, Won-Young Lee, Jongmin Kim, Sanghyuk Yoon, Baekkyu Choi, Seokhong Kwon, Joon-Young Park, Seung-Jun Bae, Yong-Cheol Bae, Jung-Hwan Choi, Seong-Jin Jang, Gyo-Young Jin:
A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. VLSIC 2015: 182- - 2014
- [j9]Sang-Hye Chung, Young-Ju Kim, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Lee-Sup Kim:
A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 153-157 (2014) - [j8]Il-Min Yi
A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 987-991 (2014) - [c12]Tae-Young Oh, Hoeju Chung, Young-Chul Cho, Jang-Woo Ryu, Kiwon Lee, Changyoung Lee, Jin-Il Lee, Hyoung-Joo Kim, Min-Soo Jang, Gong-Heum Han, Kihan Kim, Daesik Moon, Seung-Jun Bae, Joon-Young Park, Kyung-Soo Ha, Jaewoong Lee, Su-Yeon Doo, Jung-Bum Shin, Chang-Ho Shin, Kiseok Oh, Doo-Hee Hwang, Taeseong Jang, Chulsung Park, Kwang-Il Park, Jung-Bae Lee, Joo-Sun Choi:
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation. ISSCC 2014: 430-431 - 2013
- [c11]Ji-Hwan Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, Lee-Sup Kim:
An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme. ISSCC 2013: 410-411 - 2012
- [c10]Il-Min Yi, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park:
An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits. ISOCC 2012: 192-195 - [c9]Young-Sik Kim, Seon-Kyoo Lee
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. ISSCC 2012: 136-138 - 2011
- [j7]Seung-Jun Bae, JaeSheung Shin:
Performance of greedy policies for downlink scheduling in networks with relay stations. IEICE Electron. Express 8(3): 175-181 (2011) - [j6]Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. IEEE J. Solid State Circuits 46(1): 107-118 (2011) - [j5]Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park:
A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface. IEEE J. Solid State Circuits 46(9): 2053-2063 (2011) - [c8]Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. ISSCC 2011: 498-500 - 2010
- [c7]Jun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park:
A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel. CICC 2010: 1-4 - [c6]Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. ISSCC 2010: 434-435
2000 – 2009
- 2009
- [j4]Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim:
A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN. IEEE J. Solid State Circuits 44(11): 3146-3162 (2009) - [j3]Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park:
A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1645-1656 (2009) - [c5]Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim:
A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. ISSCC 2009: 138-139 - 2008
- [j2]Seung-Jun Bae, Kwang-Il Park, Jeong-Don Ihm, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Yoon-Sik Park, Min-Sang Park, Hong-Kyong Lee, Sam-Young Bang, Gil-Shin Moon, Seokwon Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. IEEE J. Solid State Circuits 43(1): 121-131 (2008) - [c4]Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Jae-Yoon Sim, Hong-June Park:
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration. ISSCC 2008: 112-113 - [c3]Seung-Jun Bae, Young-Soo Sohn, Kwang-Il Park, Kyoung-Ho Kim, Dae-Hyun Chung, Jingook Kim, Si-Hong Kim, Min-Sang Park, Jae-Hyung Lee, Sam-Young Bang, Ho-Kyung Lee, In-Soo Park, Jae-Sung Kim, Dae-Hyun Kim
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. ISSCC 2008: 278-279 - 2007
- [c2]Jeong-Don Ihm, Seung-Jun Bae, Kwang-Il Park, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Ho-Kyung Lee, Min-Sang Park, Sam-Young Bang, Mi-Jin Lee, Gil-Shin Moon, Young-Wook Jang, Suk-Won Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. ISSCC 2007: 492-617 - 2005
- [j1]Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Hong-June Park:
A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme. IEEE J. Solid State Circuits 40(5): 1119-1129 (2005) - 2003
- [c1]Young-Soo Sohn, Seung-Jun Bae, Hong-June Park, Changhyun Kim, Soo-In Cho:
A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation. CICC 2003: 473-476
Coauthor Index
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