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Tadahiko Sugibayashi
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2020 – today
- 2022
- [j22]Xu Bai, Ryusuke Nebashi, Makoto Miyamura, Kazunori Funahashi, Naoki Banno, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
:
28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation. IEICE Trans. Electron. 105-C(10): 627-630 (2022) - [j21]Xu Bai
Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation. IEEE J. Solid State Circuits 57(7): 2250-2262 (2022) - 2020
- [c17]Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS. FPL 2020: 323-327 - [c16]Koichiro Okamoto, Ryusuke Nebashi, Naoki Banno, Xu Bai, Hideaki Numata, Noriyuki Iguchi, Makoto Miyamura, Hiromitsu Hada, Kazunori Funahashi, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
ON-state retention of Atom Switch eNVM for IoT/AI Inference Solution. IRPS 2020: 1-4 - [c15]Masanori Hashimoto
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504
2010 – 2019
- 2018
- [j20]Hiroki Hihara
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10(4): 119-122 (2018) - [j19]Hiroyuki Ochi
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - 2017
- [j18]Makoto Miyamura, Toshitsugu Sakamoto, Xu Bai, Yukihide Tsuji
NanoBridge-Based FPGA in High-Temperature Environments. IEEE Micro 37(5): 32-42 (2017) - 2016
- [j17]Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. 26(1-2): 125-140 (2016) - [c14]Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL 2016: 1-4 - [c13]Yukihide Tsuji
A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond. VLSI Circuits 2016: 1-2 - 2015
- [j16]Masanori Natsui
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50(2): 476-489 (2015) - 2014
- [j15]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross:
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 460-474 (2014) - [j14]Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11(10): 20140297 (2014) - [j13]Daisuke Suzuki, Noboru Sakimura, Masanori Natsui
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11(13): 20140296 (2014) - [c12]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS 2014: 1588-1591 - [c11]Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL 2014: 220-225 - [c10]Noboru Sakimura, Yukihide Tsuji
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC 2014: 184-185 - 2013
- [j12]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. Inf. Media Technol. 8(2): 262-269 (2013) - [j11]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 6: 52-59 (2013) - [c9]Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON 2013: 1-4 - [c8]Masanori Natsui
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS 2013: 105-109 - [c7]Masanori Natsui
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC 2013: 194-195 - 2012
- [j10]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A non-volatile reconfigurable offloader for wireless sensor nodes. SIGARCH Comput. Archit. News 40(5): 87-92 (2012) - [c6]Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974 - 2011
- [c5]Makoto Miyamura, Shogo Nakaya, Munehiro Tada
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. ISSCC 2011: 228-229
2000 – 2009
- 2009
- [j9]Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai:
Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros. IEICE Trans. Electron. 92-C(4): 417-422 (2009) - [j8]Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai:
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs. IEEE J. Solid State Circuits 44(8): 2244-2250 (2009) - [c4]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami
A 90nm 12ns 32Mb 2T1MTJ MRAM. ISSCC 2009: 462-463 - 2008
- [c3]Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai:
Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs. CICC 2008: 355-358 - 2007
- [j7]Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara:
Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. IEICE Trans. Electron. 90-C(2): 531-535 (2007) - [j6]Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai:
MRAM Applications Using Unlimited Write Endurance. IEICE Trans. Electron. 90-C(10): 1936-1940 (2007) - [j5]Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo
MRAM Cell Technology for Over 500-MHz SoC. IEEE J. Solid State Circuits 42(4): 830-838 (2007) - [j4]Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo
A 16-Mb Toggle MRAM With Burst Modes. IEEE J. Solid State Circuits 42(11): 2378-2385 (2007) - 2006
- [c2]Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda:
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. ISSCC 2006: 477-486 - 2003
- [c1]Tsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda:
Resistance ratio read (R3) architecture for a burst operated 1.5V MRAM macro. CICC 2003: 399-402 - 2000
- [j3]Takashi Okuda, Isao Naritake, Tadahiko Sugibayashi, Yuji Nakajima, Tatsunori Murotani:
A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor. IEEE J. Solid State Circuits 35(8): 1153-1158 (2000)
1990 – 1999
- 1999
- [j2]Satoshi Utsugi, Masami Hanyu, Yoshinori Muramatsu, Tadahiko Sugibayashi:
Noncomplimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAM. IEEE J. Solid State Circuits 34(10): 1391-1394 (1999) - 1995
- [j1]Tadahiko Sugibayashi, Isao Naritake, Satoshi Utsugi, Kentaro Shibahara, Ryuichi Oikawa, Hidemitsu Mori, Shouichi Iwao, Tatsunori Murotani, Kuniaki Koyama, Shinichi Fukuzawa, Toshiro Itani, Kunihiko Kasama, Takashi Okuda, Shuichi Ohya, Masaki Ogawa:
A 1-Gb DRAM for file applications. IEEE J. Solid State Circuits 30(11): 1277-1280 (1995)
Coauthor Index
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