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Somnath Paul
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2020 – today
- 2023
- [c40]Yufeng Gu
, Arun Subramaniyan
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. ISCA 2023: 25:1-25:15 - 2021
- [j26]Sriram R. Vangal
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 843-856 (2021) - [c39]Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy
GenomicsBench: A Benchmark Suite for Genomics. ISPASS 2021: 1-12 - 2020
- [j25]Abdollah Alhevaz
On the sum of the distance signless Laplacian eigenvalues of a graph and some inequalities involving them. Discret. Math. Algorithms Appl. 12(1): 2050006:1-2050006:17 (2020) - [c38]Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. VLSI Circuits 2020: 1-2 - [c37]Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j24]Pascal Andreas Meinerzhagen
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - 2018
- [j23]Abdollah Alhevaz
On the distance signless Laplacian spectral radius and the distance signless Laplacian energy of graphs. Discret. Math. Algorithms Appl. 10(3): 1850035:1-1850035:19 (2018) - [j22]Somnath Paul
The spectra of a new join of graphs. Discret. Math. Algorithms Appl. 10(6): 1850074:1-1850074:15 (2018) - [j21]Somnath Paul
Conjugate Laplacian matrices of a graph. Discret. Math. Algorithms Appl. 10(6): 1850082:1-1850082:9 (2018) - [c36]Bruno U. Pedroni, Sadique Sheik, Hesham Mostafa, Somnath Paul, Charles Augustine, Gert Cauwenberghs
Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting. BioCAS 2018: 1-4 - [c35]Pascal Meinerzhagen, Carlos Tokunaga
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - 2017
- [j20]Dongyeob Shin, Jongsun Park
Adaptive ECC for Tailored Protection of Nanoscale Memory. IEEE Des. Test 34(6): 84-93 (2017) - [j19]Robert Karam
Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications. ACM J. Emerg. Technol. Comput. Syst. 13(3): 34:1-34:24 (2017) - [j18]Somnath Paul
A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. IEEE J. Solid State Circuits 52(4): 961-971 (2017) - [j17]Wenchao Qian
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 177-188 (2017) - [c34]Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis:
Event-driven random backpropagation: Enabling neuromorphic deep learning machines. ISCAS 2017: 1-4 - [i4]Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs:
Membrane-Dependent Neuromorphic Learning Rule for Unsupervised Spike Pattern Detection. CoRR abs/1701.01495 (2017) - [i3]Georgios Detorakis, Sadique Sheik, Charles Augustine, Somnath Paul, Bruno U. Pedroni, Nikil D. Dutt, Jeffrey L. Krichmar, Gert Cauwenberghs, Emre Neftci:
Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning. CoRR abs/1709.10205 (2017) - 2016
- [j16]Somnath Paul
On distance and distance Laplacian spectra of corona of two graphs. Discret. Math. Algorithms Appl. 8(1): 1650007:1-1650007:13 (2016) - [j15]Christopher Babecki
An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications. IEEE Trans. Computers 65(10): 3196-3202 (2016) - [c33]Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs
Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection. BioCAS 2016: 164-167 - [c32]Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
Forward table-based presynaptic event-triggered spike-timing-dependent plasticity. BioCAS 2016: 580-583 - [c31]Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah
Synaptic sampling in hardware spiking neural networks. ISCAS 2016: 2090-2093 - [c30]Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James W. Tschanz, Vivek De:
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - [i2]Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs:
Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity. CoRR abs/1607.03070 (2016) - [i1]Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis:
Event-driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines. CoRR abs/1612.05596 (2016) - 2015
- [j14]Kaushik Roy, Deliang Fan, Xuanyao Fong
Exploring Spin Transfer Torque Devices for Unconventional Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 5-16 (2015) - [j13]Somnath Paul, Aswin Raghav Krishna, Wenchao Qian, Robert Karam, Swarup Bhunia
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1005-1016 (2015) - 2014
- [j12]Milan Nath, Somnath Paul
On the Minimal Distance spectral radius in the Class of bicyclic graphs. Discret. Math. Algorithms Appl. 6(1) (2014) - [j11]Milan Nath, Somnath Paul
A note on the Distance spectral radius of some graphs. Discret. Math. Algorithms Appl. 6(1) (2014) - [j10]Anandaroop Ghosh, Somnath Paul, Jongsun Park
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1314-1327 (2014) - [j9]Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2449-2461 (2014) - [c29]Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri:
Energy-efficient hardware acceleration through computing in the memory. DATE 2014: 1-6 - [c28]Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
Robust low-power reconfigurable computing with a variation-aware preferential design approach. ICICDT 2014: 1-6 - 2013
- [j8]Milan Nath, Somnath Paul
Graph Transformation and Distance spectral radius. Discret. Math. Algorithms Appl. 5(3) (2013) - [j7]Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis G. Wolff, Christos A. Papachristou
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis. IEEE Trans. Computers 62(11): 2183-2195 (2013) - [c27]Abhishek Basak, Somnath Paul, Jangwon Park, Jongsun Park
Reconfigurable ECC for adaptive protection of memory. MWSCAS 2013: 1085-1088 - [c26]Somnath Paul, Abhijit Dana, Soumya Pandit:
An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design. VDAT 2013: 128-137 - 2012
- [j6]Somnath Paul
On the Maximal Distance spectral radius in a Class of bicyclic Graphs. Discret. Math. Algorithms Appl. 4(4) (2012) - [c25]Lei Wang, Somnath Paul, Swarup Bhunia
Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory. VLSI Design 2012: 340-345 - [c24]Anandaroop Ghosh, Somnath Paul, Swarup Bhunia
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks. VLSI Design 2012: 424-429 - 2011
- [j5]Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 369-380 (2011) - [j4]Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. IEEE Trans. Computers 60(1): 20-34 (2011) - [j3]Somnath Paul, Swarup Bhunia
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1368-1379 (2011) - [c23]Somnath Paul, Swarup Bhunia:
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). FPGA 2011: 283 - [c22]Xinmu Wang, Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing. NANOARCH 2011: 210-217 - 2010
- [j2]Somnath Paul, Hamid Mahmoodi
Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection. ACM Trans. Design Autom. Electr. Syst. 15(2): 19:1-19:34 (2010) - [c21]Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis G. Wolff, Christos A. Papachristou
System level self-healing for parametric yield and reliability improvement under power bound. AHS 2010: 52-58 - [c20]Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. HOST 2010: 13-18 - [c19]Somnath Paul, Swarup Bhunia
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. ISLPED 2010: 37-42
2000 – 2009
- 2009
- [j1]Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, Swarup Bhunia
Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping. IET Comput. Digit. Tech. 3(6): 609-624 (2009) - [c18]Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou
MERO: A Statistical Approach for Hardware Trojan Detection. CHES 2009: 396-410 - [c17]Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
A circuit-software co-design approach for improving EDP in reconfigurable frameworks. ICCAD 2009: 109-112 - [c16]Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
A variation-aware preferential design approach for memory based reconfigurable computing. ICCAD 2009: 180-183 - [c15]Somnath Paul, Swarup Bhunia
Computing with nanoscale memory: Model and architecture. NANOARCH 2009: 1-6 - 2008
- [c14]Somnath Paul, Swarup Bhunia
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. ASP-DAC 2008: 77-82 - [c13]Seetharam Narasimhan, Somnath Paul, Swarup Bhunia:
Collective computing based on swarm intelligence. DAC 2008: 349-350 - [c12]Somnath Paul, Swarup Bhunia:
Reconfigurable computing using content addressable memory for improved performance and resource usage. DAC 2008: 786-791 - [c11]Yu Zhou, Somnath Paul, Swarup Bhunia
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. DATE 2008: 98-103 - [c10]Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia
On-Demand Transparency for Improving Hardware Trojan Detectability. HOST 2008: 48-50 - [c9]Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. ICCAD 2008: 589-592 - [c8]Yu Zhou, Somnath Paul, Swarup Bhunia
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. ISQED 2008: 861-866 - [c7]Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. VLSI Design 2008: 441-446 - 2007
- [c6]Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia
Low-overhead design technique for calibration of maximum frequency at multiple operating points. ICCAD 2007: 401-404 - [c5]Somnath Paul, Swarup Bhunia
Memory based computation using embedded cache for processor yield and reliability improvement. ICCD 2007: 341-346 - [c4]Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. IOLTS 2007: 29-36 - [c3]Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. ISQED 2007: 755-760 - [c2]Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. VTS 2007: 455-460
1990 – 1999
- 1998
- [c1]Pradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta:
Hardware/Software Co-design of a High-end Mixed Signal Microcontroller. VLSI Design 1998: 91-96
Coauthor Index
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