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VTS 2014: Napa, CA, USA
- 32nd IEEE VLSI Test Symposium, VTS 2014, Napa, CA, USA, April 13-17, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-2611-4
- Manolis Kaliorakis, Mihalis Psarakis, Nikos Foutris, Dimitris Gizopoulos:
Accelerated online error detection in many-core microprocessor architectures. 1-6 - Abhishek Basak, Yu Zheng, Swarup Bhunia
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Active defense against counterfeiting attacks through robust antifuse-based on-chip locks. 1-6 - Ya-Ru Wu, Yi-Keng Hsieh, Po-Chih Ku, Liang-Hung Lu:
A built-in gain calibration technique for RF low-noise amplifiers. 1-6 - Abdulazim Amouri, Jochen Hepp, Mehdi Baradaran Tahoori:
Self-heating thermal-aware testing of FPGAs. 1-6 - Lu Wang, Xutao Wang, Milad Maleki, Bao Liu:
Power/ground supply voltage variation-aware delay test pattern generation. 1-6 - Anne Gattiker:
Unstructured text: Test analysis techniques applied to non-test problems. 1-4 - Atefe Dalirsani, Michael E. Imhof, Hans-Joachim Wunderlich:
Structural Software-Based Self-Test of Network-on-Chip. 1-6 - John Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar:
Innovative practices session 3C: Solving today's test challenges. 1 - Rohit Kapur, Irith Pomeranz:
Innovative practices session 10C: Advances in DFT and compression. 1 - Sule Ozev, Bertan Bakkaloglu:
Special session 4B: Panel: Testing and calibration for power management circuits. 1 - Kai Hu, Tsung-Yi Ho
Test generation and design-for-testability for flow-based mVLSI microfluidic biochips. 1-6 - Tao Liu, Chao Fu, Sule Ozev, Bertan Bakkaloglu
A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters. 1-6 - Sabyasachi Deyati, Barry John Muldrey
Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits. 1-6 - Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang:
A 4-GHz universal high-frequency on-chip testing platform for IP validation. 1-6 - Gurgen Harutyunyan, Grigor Tshagharyan, Valery A. Vardanian, Yervant Zorian:
Fault modeling and test algorithm creation strategy for FinFET-based memories. 1-6 - Yen-Tzu Lin, Brady Benware, Brian Stine, Azeez Bhavnagarwala:
Innovative practices session 2C: Advanced in yield learning. 1 - Xiaolei Cai, Emil Gizdarski, Dan Landau:
A shared memory based parallel diagnosis system. 1-6 - Jae Woong Jeong, Sule Ozev, Friedrich Taenzler, Hui-Chuan Chao:
Development and empirical verification of an accuracy model for the power down leakage tests. 1-6 - Haralampos-G. D. Stratigopoulos, Stephen Sunter:
Efficient Monte Carlo-based analog parametric fault modelling. 1-6 - Sen-Wen Hsiao, Chung-Chun Chen, Randy Caplan, Jeff Galloway, Blake Gray, Abhijit Chatterjee:
Phase-locked loop design with SPO detection and charge pump trimming for reference spur suppression. 1-6 - Li Xu, Degang Chen:
Accurate and efficient method of jitter and noise separation and its application to ADC testing. 1-5 - Shahrzad Mirkhani, Jacob A. Abraham:
Fast evaluation of test vector sets using a simulation-based statistical metric. 1-6 - Irith Pomeranz:
Fault simulation with test switching for static test compaction. 1-6 - Doohwang Chang, Sule Ozev, Bertan Bakkaloglu
Reliability enhancement using in-field monitoring and recovery for RF circuits. 1-6 - Carolina Metzler, Aida Todri-Sanial
TSV aware timing analysis and diagnosis in paths with multiple TSVs. 1-6 - John M. Carulli:
Special session 11B: ITRS adaptive test update. 1 - Zhiqiang Liu, You Li, Randall L. Geiger, Degang Chen:
Auto-identification of positive feedback loops in multi-state vulnerable circuits. 1-5 - Ran Wang, Krishnendu Chakrabarty
At-speed interconnect testing and test-path optimization for 2.5D ICs. 1-6 - Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche:
Built-in self-test for manufacturing TSV defects before bonding. 1-6 - Soonyoung Cha, Chang-Chih Chen, Taizhi Liu, Linda S. Milor
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements. 1-6 - Amitava Majumdar, Suriya Natarajan, Stephen K. Sunter, Prashant Goteti, Ke Huang:
Innovative practices session 4C: Disruptive solutions in the non-digital world. 1 - Allan Ecker, Mani Soma:
A method for phase noise extraction from data communication. 1-6 - Jennifer Dworak:
Special session 4A: Elevator talks. 1 - Sounil Biswas, John M. Carulli, Dragoljub Gagi Drmanac, Arpan Bhattacherjee:
Innovative practices session 5C: Machine learning and data analysis in test. 1 - Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri
Detection, diagnosis, and repair of faults in memristor-based memories. 1-6 - Thomas Moon, Hyun Woo Choi, David C. Keezer
Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms. 1-6 - Stephen K. Sunter, Steve Comen, Paul Berndt, Ram Rajamani:
Innovative practices session 7C: Reduced pin-count testing - How low can we go? 1 - Alodeep Sanyal, Yanjing Li:
Special session 11C: Young professionals in test - Elevator talks. 1 - Xian Wang, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee:
Alternative "safe" test of hysteretic power converters. 1-6 - Franco Stellari, Peilin Song, Herschel A. Ainspan:
Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements. 1-6 - Eshan Singh:
Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking. 1-6 - Yongquan Fan, Anant Verma, David S. Trager, Ramin K. Poorfard, John Janney, Sandeep Kumar:
Accelerating capture of infrequent errors on ATE for silicon TV tuners. 1-6 - Alodeep Sanyal, Yanjing Li, Yervant Zorian:
Special session 12C: Young professionals in test - Town meeting. 1 - Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane:
Innovative practices session 1C: Existing/emerging low power techniques. 1 - Hao-Yu Yang, Chen-Wei Lin, Chao-Ying Huang, Ching-Ho Lu, Chen-An Lai, Mango Chia-Tso Chao, Rei-Fu Huang:
Testing methods for a write-assist disturbance-free dual-port SRAM. 1-6 - Breeta SenGupta, Erik Larsson
Test planning and test access mechanism design for stacked chips using ILP. 1-6 - Bozena Kaminska, Bernard Courtois, Chris Bailey:
New topic session 2B: Co-design and reliability of power electronic modules - Current status and future challenges. 1 - Andres Viveros-Wacher, Ricardo Alejos, Liliana Alvarez, Israel Diaz-Castro, Brenda Marcial, Gaston Motola-Acuna, Edgar-Andrei Vega-Ochoa:
SMV methodology enhancements for high speed I/O links of SoCs. 1-5 - Tengteng Zhang, Duncan M. Hank Walker:
Improved power supply noise control for pseudo functional test. 1-6 - Woongrae Kim, Linda Milor
Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells. 1-6 - Chao Han, Adit D. Singh:
Improving CMOS open defect coverage using hazard activated tests. 1-6 - Jifeng Chen, LeRoy Winemberg, Mohammad Tehranipoor:
Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field tests. 1-6 - Mohamed Metwally, Nicholai L'Esperance, Tian Xia, Mustapha Slamani:
Continuous wave radar circuitry testing using OFDM technique. 1-6 - Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Terri S. Fiez, Mike Peng Li:
Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test. 1 - Mukesh Agrawal, Krishnendu Chakrabarty
Test-time optimization in NOC-based manycore SOCs using multicast routing. 1-6 - Cheng-Hung Wu, Kuen-Jong Lee, Wei-Cheng Lien
An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model. 1-6 - Michele Portolan, Michail Maniatakos:
Special session 8A: E.J. McCluskey Doctoral Thesis Award semi-final. 1 - Fangming Ye, Farshad Firouzi, Yang Yang, Krishnendu Chakrabarty
On-chip voltage-droop prediction using support-vector machines. 1-6 - Pasquale Ranone, Giovanna Turvani
Fault tolerant nanoarray circuits: Automatic design and verification. 1-6 - Bozena Kaminska, Bernard Courtois, Mary Ann Maher:
New topic session 7B: Challenges and opportunities in test and design for test (DFT) of MEMS sensors. 1 - Dean Collins, Ramesh Karri
Hot topic session 12A: Split manufacturing - IARPA's TIC program. 1-2 - C. J. Clark, Víctor H. Champac:
Hot topic session 12B: Stay relevant with standards-based DFT. 1 - Irith Pomeranz:
On the use of multi-cycle tests for storage of two-cycle broadside tests. 1-6 - Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players? 1-2 - Suriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran:
Hot topic session 9C: Test and fault tolerance for emerging memory technologies. 1 - Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
Quality versus cost analysis for 3D Stacked ICs. 1-6
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