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Víctor H. Champac
Víctor H. Champac Vilela
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- affiliation: National Institute of Astrophysics, Optics and Electronics, Puebla, Mexico
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2020 – today
- 2024
- [j35]Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura:
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations. J. Electron. Test. 40(1): 75-86 (2024) - [c59]Leonardo Miceli, Elena-Ioana Vatajelu, Víctor H. Champac:
Fault Analysis for a MTJ-based Spiking Neural Network. LATS 2024: 1-6 - 2023
- [j34]Freddy Forero
, Víctor H. Champac, Michel Renovell
B-open Defect: A Novel Defect Model in FinFET Technology. ACM J. Emerg. Technol. Comput. Syst. 19(1): 3:1-3:19 (2023) - [c58]Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli:
A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates. LATS 2023: 1-6 - 2022
- [c57]Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura:
Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations. LATS 2022: 1-6 - 2021
- [j33]Víctor H. Champac, Javier Mesalles, Hector Villacorta, Fabian Vargas:
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell. J. Electron. Test. 37(3): 369-382 (2021) - 2020
- [j32]Ivan D. Meza-Ibarra, Víctor H. Champac, Roberto Gómez-Fuentes
Identification of Logic Paths Influenced by Severe Coupling Capacitances. J. Electron. Test. 36(6): 731-741 (2020) - [c56]Zahira Perez, Javier Mesalles, Hector Villacorta, Fabian Vargas, Víctor H. Champac:
Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells. LATS 2020: 1-6
2010 – 2019
- 2019
- [j31]Andres F. Gomez, Víctor H. Champac:
An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects. J. Electron. Test. 35(1): 87-100 (2019) - [j30]Freddy Forero
Modeling and Detectability of Full Open Gate Defects in FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2180-2190 (2019) - [c55]Freddy Forero, Michel Renovell, Víctor H. Champac:
B-open: A New Defect in Nanometer Technologies due to SADP Process. ETS 2019: 1-2 - [c54]Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. LATS 2019: 1-6 - [c53]Ivan D. Meza-Ibarra, Víctor H. Champac, Roberto Gómez-Fuentes, Jose R. Noriega-Luna, A. Vera-Marquina:
Identification of Logic Paths Influenced by Severe Coupling Capacitances. LATS 2019: 1-6 - 2018
- [j29]Freddy Forero
Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. J. Electron. Test. 34(2): 123-134 (2018) - [j28]Andres F. Gomez, Víctor H. Champac:
Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects. ACM Trans. Design Autom. Electr. Syst. 23(3): 27:1-27:21 (2018) - [c52]Andres F. Gomez, Roberto Gómez, Víctor H. Champac:
A metric-guided gate-sizing methodology for aging guardband reduction. LATS 2018: 1-6 - [c51]Andres F. Gomez, Freddy Forero, Kaushik Roy, Víctor H. Champac:
Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. VLSI-SoC 2018: 65-70 - [c50]Zahira Perez
An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations. VLSI-SoC 2018: 77-82 - [c49]Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy:
Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. VLSI-SoC (Selected Papers) 2018: 207-231 - 2017
- [c48]Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac:
Analysis of short defects in FinFET based logic cells. LATS 2017: 1-6 - 2016
- [j27]Hector Villacorta, Jaume Segura
Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. J. Electron. Test. 32(3): 307-314 (2016) - [j26]Freddy Forero, Andres F. Gomez, Víctor H. Champac:
Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage. J. Low Power Electron. 12(4): 395-402 (2016) - [j25]Andres F. Gomez, Felipe Lavratti, Guilherme Medeiros Machado, M. Sartori, Letícia Maria Veiras Bolzani, Víctor H. Champac, Fabian Vargas:
Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations. Microelectron. Reliab. 67: 150-158 (2016) - [j24]Jesús Moreno, Michel Renovell, Víctor H. Champac:
Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 378-382 (2016) - [j23]Andres F. Gomez, Víctor H. Champac:
Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2438-2448 (2016) - [c47]Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac:
Behavior and test of open-gate defects in FinFET based cells. ETS 2016: 1-6 - [c46]Andres F. Gomez, Víctor H. Champac:
Critical path selection under NBTI/PBTI aging for adaptive frequency tuning. EWDTS 2016: 1-4 - [c45]Freddy Forero, Andres F. Gomez, Víctor H. Champac:
A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage. LATS 2016: 81-86 - 2015
- [j22]Hector Villacorta, Jose Luis Garcia-Gervacio, Jaume Segura
Low VDD and body bias conditions for testing bridge defects in the presence of process variations. Microelectron. J. 46(5): 398-403 (2015) - [j21]Jose Luis Garcia-Gervacio, Alejandro Nocua
Screening small-delay defects using inter-path correlation to reduce reliability risk. Microelectron. Reliab. 55(6): 1005-1011 (2015) - [c44]Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal:
Message from the LATS2015 Chairs. LATS 2015: 1 - [c43]Andres F. Gomez, Víctor H. Champac:
Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability. LATS 2015: 1-6 - [c42]Hector Villacorta, Roberto Gómez, Sebastià A. Bota, Jaume Segura
Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. LATS 2015: 1-6 - [c41]Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez:
Circuit performance optimization for local intra-die process variations using a gate selection metric. VLSI-SoC 2015: 165-170 - [c40]Andres F. Gomez, Víctor H. Champac:
A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. VLSI-SoC 2015: 297-302 - [c39]Andres F. Gomez, Leticia B. Poehls, Fabian Vargas, Víctor H. Champac:
An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging. VTS 2015: 1-6 - 2014
- [j20]Víctor H. Champac, Hector Villacorta, Nestor Hernandez, Joan Figueras:
Skew violation verification in digital interconnect signals based on signal addition. IEICE Electron. Express 11(15): 20140201 (2014) - [c38]Jose Luis Garcia-Gervacio, Jaime Martínez-Castillo
Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies. LATW 2014: 1-6 - [c37]Hector Villacorta, Jaume Segura
Analysis of fin height on FinFET SRAM cell hardening. MWSCAS 2014: 671-674 - [c36]C. J. Clark, Víctor H. Champac:
Hot topic session 12B: Stay relevant with standards-based DFT. VTS 2014: 1 - 2013
- [j19]Hector Villacorta, Charles F. Hawkins, Víctor H. Champac, Jaume Segura
Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. IEEE Des. Test 30(6): 70-79 (2013) - [j18]Julio César Vázquez, Víctor H. Champac, Jorge Semião
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion. J. Electron. Test. 29(3): 289-299 (2013) - [c35]Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota
Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. LATW 2013: 1-6 - 2012
- [j17]Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barceló
Testing of Stuck-Open Faults in Nanometer Technologies. IEEE Des. Test Comput. 29(4): 80-91 (2012) - [j16]Jackson Pachito, Celestino V. Martins, Bruno Jacinto, Jorge Semião
Aging-Aware Power or Frequency Tuning With Predictive Fault Detection. IEEE Des. Test Comput. 29(5): 27-36 (2012) - [j15]Hector Villacorta, Víctor H. Champac, Sebastià A. Bota
Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test. Microelectron. Reliab. 52(11): 2799-2804 (2012) - [c34]Jesús Moreno, Víctor H. Champac, Michel Renovell:
Low voltage testing for interconnect opens under process variations. LATW 2012: 1-6 - [c33]Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu:
Small-delay defects detection under process variation using Inter-Path Correlation. VTS 2012: 127-132 - 2011
- [j14]Jose Luis Garcia-Gervacio, Víctor H. Champac:
Computing the Detection Probability for Small Delay Defects of Nanometer ICs. J. Electron. Test. 27(6): 741-752 (2011) - [j13]Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electron. 7(4): 529-530 (2011) - [c32]Jesús Moreno, Víctor H. Champac, Michel Renovell:
A new methodology for realistic open defect detection probability evaluation under process variations. VTS 2011: 184-189 - [c31]Celestino V. Martins, Jorge Semião
Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. VTS 2011: 203-208 - 2010
- [j12]Víctor H. Champac, Victor Avendaño, Joan Figueras:
Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 256-269 (2010) - [c30]Julio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira:
Programmable aging sensor for automotive safety-critical applications. DATE 2010: 618-621 - [c29]Jose Luis Garcia-Gervacio, Víctor H. Champac:
Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. ETS 2010: 126-131 - [c28]Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis
Predictive error detection by on-line aging monitoring. IOLTS 2010: 9-14 - [c27]Hector Villacorta, Víctor H. Champac, Chuck Hawkins, Jaume Segura
Reliability analysis of small delay defects in vias located in signal paths. LATW 2010: 1-6 - [c26]Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis
Low-sensitivity to process variations aging sensor for automotive safety-critical applications. VTS 2010: 238-243
2000 – 2009
- 2009
- [c25]Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel C. Teixeira
Built-in aging monitoring for safety-critical applications. IOLTS 2009: 9-14 - [c24]Jose Luis Garcia-Gervacio, Víctor H. Champac:
Detectability analysis of small delays due to resistive opens considering process variations. IOLTS 2009: 195-197 - [c23]Roberto Gómez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
A modern look at the CMOS stuck-open fault. LATW 2009: 1-6 - [c22]Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
Stuck-Open Fault Leakage and Testing in Nanometer Technologies. VTS 2009: 315-320 - 2008
- [j11]Roberto Gómez, Alejandro Girón, Víctor H. Champac:
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines. J. Electron. Test. 24(6): 529-538 (2008) - [c21]Daniel Iparraguirre-Cardenas, Jose Luis Garcia-Gervacio, Víctor H. Champac:
A design methodology for logic paths tolerant to local intra-die variations. ISCAS 2008: 596-599 - [c20]Nestor Hernandez, Víctor H. Champac:
Testing Skew and Logic Faults in SoC Interconnects. ISVLSI 2008: 151-156 - 2007
- [j10]Antonio Zenteno Ramírez, Guillermo Espinosa, Víctor H. Champac:
Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 572-577 (2007) - 2005
- [c19]Roberto Gómez, Alejandro Girón, Víctor H. Champac:
Test of Interconnection Opens Considering Coupling Signals. DFT 2005: 247-258 - [c18]Víctor H. Champac, Antonio Zenteno, José L. Garcia:
Testing of resistive opens in CMOS latches and flip-flops. ETS 2005: 34-40 - 2004
- [j9]Fabian Vargas, Víctor H. Champac:
Guest Editorial. J. Electron. Test. 20(4): 331-332 (2004) - [c17]Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs:
Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium 2004: 460-463 - [c16]Victor Avendaño, Víctor H. Champac, Joan Figueras:
Signal integrity verification using high speed monitors. ETS 2004: 114-119 - [c15]Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac Vilela:
An improved technique to increase noise-tolerance in dynamic digital circuits. ISCAS (2) 2004: 489-492 - [c14]Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac Vilela:
The noise immunity of dynamic digital circuits with technology scaling. ISCAS (2) 2004: 493-496 - 2003
- [j8]Víctor H. Champac, Ingrid Jansch-Pôrto:
Guest Editorial. J. Electron. Test. 19(1): 11 (2003) - [c13]Victor Avendaño, Víctor H. Champac, Joan Figueras:
Signal integrity loss in bus lines due to open shielding defects. ETW 2003: 79-84 - 2002
- [c12]Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac, Alejandro Díaz-Sánchez:
A new technique for noise-tolerant pipelined dynamic digital circuits. ISCAS (4) 2002: 185-188 - [c11]Antonio Zenteno, Víctor H. Champac, Jaime Ramírez-Angulo:
Behavior Analysis and Testing of Resistive Opens in the Clock Circuitry of Memory Elements. LATW 2002: 205-211 - 2001
- [j7]Marcelo Lubaszewski, Víctor H. Champac:
Guest Editorial. J. Electron. Test. 17(2): 83-84 (2001) - [j6]Antonio Zenteno, Víctor H. Champac, Joan Figueras:
Detectability Conditions of Full Opens in the Interconnections. J. Electron. Test. 17(2): 85-95 (2001) - [c10]Anotnio Zenteno, Víctor H. Champac, Joan Figueras:
Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain. LATW 2001: 38-44 - [c9]Víctor H. Champac, Victor Avendaño, Gordana Jovanovic-Dolecek:
Test of Data Retention Faults Sensing the Bit Line with a DFT Bases Differential Amplifier. LATW 2001: 273-276 - [c8]Antonio Zenteno, Víctor H. Champac:
Resistive Opens in a Class of CMOS Latches: Analysis and DFT. VTS 2001: 138-144 - 2000
- [j5]Gordana Jovanovic-Dolecek
CGTDEMO - educational software for the central limit theorem. ACM SIGCSE Bull. 32(2): 46-48 (2000) - [c7]Antonio Zenteno, Víctor H. Champac, Joan Figueras:
Detectability Dependency on Test Generation Process for Interconnection Opens. LATW 2000: 47-53 - [c6]Víctor H. Champac, Antonio Zenteno:
Detectability Conditions for Interconnection Open Defect. VTS 2000: 305-312
1990 – 1999
- 1999
- [j4]Víctor H. Champac, José Castillejos, Joan Figueras:
IDDQ Testing of Opens in CMOS SRAMs. J. Electron. Test. 15(1-2): 53-62 (1999) - 1998
- [c5]Arturo Sarmiento-Reyes, Miguel Ángel Gutiérrez de Anda, Víctor H. Champac:
A Graph-Oriented CAD Tool for Establishing the Topological Diagnostic Conditions of Analogue Circuits. SBCCI 1998: 179-183 - [c4]Víctor H. Champac, José Castillejos, Joan Figueras:
IDDQ Testing of Opens in CMOS SRAMs. VTS 1998: 106-111 - 1997
- [j3]Víctor H. Champac, Joan Figueras:
Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects. VLSI Design 5(3): 273-284 (1997) - 1995
- [c3]Víctor H. Champac, Joan Figueras:
Testability of floating gate defects in sequential circuits. VTS 1995: 202-207 - 1994
- [j2]Víctor H. Champac, Antonio Rubio, Joan Figueras:
Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 359-369 (1994) - 1993
- [c2]Víctor H. Champac, Antonio Rubio, Joan Figueras:
Analysis of the Floating Gate Defect in CMOS. DFT 1993: 101-108 - 1992
- [j1]Jaume A. Segura
Quiescent current analysis and experimentation of defective CMOS circuits. J. Electron. Test. 3(4): 337-348 (1992) - 1991
- [c1]Rosa Rodríguez-Montañés, Jaume A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio:
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. ITC 1991: 510-519
Coauthor Index
Letícia Maria Veiras Bolzani
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia B. Poehls
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia B. Poehls
Roberto Gómez 0001
aka: Roberto Gómez-Fuentes
aka: Roberto Gómez-Fuentes
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