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Takahiro J. Yamaguchi
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2020 – today
- 2022
- [j16]Zolboo Byambadorj
, Koji Asami
High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 378-388 (2022) - 2020
- [j15]Zolboo Byambadorj
Theoretical Analysis of Noise Figure for Modulated Wideband Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 298-308 (2020) - [j14]Zolboo Byambadorj
A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters. IEEE Trans. Circuits Syst. 67-I(12): 5561-5573 (2020) - [c57]Zolboo Byambadorj, Koji Asami, Takahiro J. Yamaguchi, Akio Higo, Masahiro Fujita, Tetsuya Iizuka:
Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing. ATS 2020: 1-6
2010 – 2019
- 2019
- [j13]Kiichi Niitsu
Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. IEICE Electron. Express 16(13): 20190218 (2019) - 2018
- [c56]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS 2018: 408-411 - 2016
- [c55]Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS 2016: 29-32 - [c54]James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada:
A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators. NEWCAS 2016: 1-4 - 2015
- [j12]Kiichi Niitsu
A CMOS PWM Transceiver Using Self-Referenced Edge Detection. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1145-1149 (2015) - [c53]Tetsuya Iizuka, Takahiro J. Yamaguchi:
Session 3 - Optical interconnect and reliability enhancement techniques. CICC 2015: 1 - [c52]Takahiro J. Yamaguchi, Katsuhiko Degawa, Masayuki Kawabata, Masahiro Ishida, Koichiro Uekusa, Mani Soma:
A new method for measuring alias-free aperture jitter in an ADC output. ITC 2015: 1-6 - 2014
- [j11]Kiichi Niitsu
A low-offset cascaded time amplifier with reconfigurable inter-stage connection. IEICE Electron. Express 11(10): 20140203 (2014) - [j10]Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada:
A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 777-780 (2014) - [c51]Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge. ATS 2014: 168-173 - [c50]James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer. ISCAS 2014: 93-96 - [c49]Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Terri S. Fiez, Mike Peng Li:
Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test. VTS 2014: 1 - 2013
- [j9]Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. J. Electron. Test. 29(6): 879-892 (2013) - [j8]Kiichi Niitsu
A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines. IEICE Trans. Electron. 96-C(6): 920-922 (2013) - [c48]Kiichi Niitsu
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. ASP-DAC 2013: 103-104 - [c47]Mike Peng Li, Takahiro J. Yamaguchi:
Electrical and photonic I/O test and debug. CICC 2013: 1-2 - [c46]James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. CICC 2013: 1-4 - [c45]Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada:
A novel test structure for measuring the threshold voltage variance in MOSFETs. ITC 2013: 1-8 - [c44]Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas:
Special session 12B: Panel post-silicon validation & test in huge variance era. VTS 2013: 1 - 2012
- [j7]Kiichi Niitsu
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation. IEEE J. Solid State Circuits 47(11): 2701-2710 (2012) - [c43]Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu
Multi-bit sigma-delta TDC architecture with self-calibration. APCCAS 2012: 671-674 - [c42]Kiichi Niitsu
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. ASP-DAC 2012: 553-554 - [c41]Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu
A New Procedure for Measuring High-Accuracy Probability Density Functions. Asian Test Symposium 2012: 185-190 - [c40]Takahiro J. Yamaguchi:
Session Summary IV: Post-Silicon Measurements and Tests: Analog Test and High-Speed I/O Test II. Asian Test Symposium 2012: 245 - [c39]Kiichi Niitsu
Post-Silicon Jitter Measurements. Asian Test Symposium 2012: 258-263 - [c38]Kiichi Niitsu
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. VLSIC 2012: 142-143 - 2011
- [j6]Tomohiko Ogawa, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Satoshi Ito, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu
Design for Testability That Reduces Linearity Testing Time of SAR ADCs. IEICE Trans. Electron. 94-C(6): 1061-1064 (2011) - [c37]Kiichi Niitsu
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation. A-SSCC 2011: 201-204 - [c36]Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada:
Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology. ICECS 2011: 220-223 - [c35]Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada:
An equivalent-time and clocked approach for continuous-time quantization. ISCAS 2011: 2529-2532 - [c34]Masato Sakurai, Kiichi Niitsu
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. ISOCC 2011: 146-149 - [c33]Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu:
Application of a continuous-time level crossing quantization method for timing noise measurements. ITC 2011: 1-10 - 2010
- [c32]Satoshi Uemori, Takahiro J. Yamaguchi, Satoshi Ito, Yohei Tan, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu
ADC linearity test signal generation algorithm. APCCAS 2010: 44-47 - [c31]Tomohiko Ogawa, Haruo Kobayashi, Yohei Tan, Satoshi Ito, Satoshi Uemori, Nobukazu Takai, Kiichi Niitsu
SAR ADC that is configurable to optimize yield. APCCAS 2010: 374-377 - [c30]Satoshi Ito, Shigeyuki Nishimura, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu
Stochastic TDC architecture with self-calibration. APCCAS 2010: 1027-1030
2000 – 2009
- 2009
- [c29]Albert Tumewu, Kazuyuki Miyazawa, Takafumi Aoki, Takahiro J. Yamaguchi, Katsuhiko Degawa, Takayuki Akita:
Phase-based alignment of two signals having partially overlapped spectra. ICASSP 2009: 3337-3340 - [c28]Takahiro J. Yamaguchi, Kiyotaka Ichiyama, X. H. Hou, Masahiro Ishida:
A robust method for identifying a deterministic jitter model in a total jitter distribution. ITC 2009: 1-10 - 2008
- [c27]Takahiro J. Yamaguchi, Masahiro Ishida:
Total Jitter Measurement for Testing HSIO Integrated SoCs. ATS 2008: 194 - [c26]Takahiro J. Yamaguchi, Masayuki Kawabata, Mani Soma, Masahiro Ishida, K. Sawami, Koichiro Uekusa:
A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB Testing. ITC 2008: 1-9 - 2007
- [c25]Takahiro J. Yamaguchi:
Top 5 Issues in Practical Testing of High-Speed Interface Devices. ATS 2007: 519 - [c24]Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma:
Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter. CICC 2007: 161-164 - [c23]Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma:
An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter. ISCAS 2007: 2798-2801 - [c22]Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma:
Data jitter measurement using a delta-time-to-voltage converter method. ITC 2007: 1-7 - [c21]Takahiro J. Yamaguchi, H. X. Hou, Koji Takayama, Dave Armstrong, Masahiro Ishida, Mani Soma:
An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test time. ITC 2007: 1-8 - 2006
- [c20]Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma:
A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter Measurement. ITC 2006: 1-8 - [c19]Takahiro J. Yamaguchi, Satoshi Iwamoto, Masahiro Ishida, Mani Soma:
A Study of Per-Pin Timing Jitter Scope. ITC 2006: 1-7 - 2005
- [c18]Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma:
A wideband low-noise ATE-based method for measuring jitter in GHz signals. ITC 2005: 10 - 2004
- [j5]Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida:
Skew measurements in clock distribution circuits using an analytic signal method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 997-1009 (2004) - [c17]Kazuyuki Maruo, Masayoshi Ichikawa, Naoto Miyamoto, Leo Karnan, Takahiro J. Yamaguchi, Koji Kotani, Tadahiro Ohmi:
A Dynamically-Reconfigurable Image Recognition Processor. IPDPS 2004 - [c16]Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai:
A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems. ITC 2004: 77-84 - [c15]Takahiro J. Yamaguchi:
Loopback or not? ITC 2004: 1434 - 2003
- [j4]Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha:
Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division. J. Electron. Test. 19(2): 183-193 (2003) - [j3]Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Toshifumi Watanabe, Tadahiro Ohmi:
Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method. IEEE Trans. Circuits Syst. II Express Briefs 50(6): 288-298 (2003) - [c14]Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha:
Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements. ITC 2003: 58-66 - [c13]Takahiro J. Yamaguchi:
Open Architecture ATE and 250 Consecutive UIs. ITC 2003: 1307 - 2002
- [j2]Takahiro J. Yamaguchi, Dong Sam Ha, Masahiro Ishida, Tadahiro Ohmi:
A Method for Compressing Test Data Based on Burrows-Wheeler Transformation. IEEE Trans. Computers 51(5): 486-497 (2002) - [c12]Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha:
Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices. Asian Test Symposium 2002: 45-48 - [c11]Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie:
A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter. ITC 2002: 717-725 - [c10]Takahiro J. Yamaguchi:
Multi-GHz interface devices should be tested using external test resources. ITC 2002: 1229 - [c9]Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha:
Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division. VTS 2002: 207-212 - 2001
- [c8]Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida:
Testing clock distribution circuits using an analytic signal method. ITC 2001: 323-331 - [c7]Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen:
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. VTS 2001: 102-110 - 2000
- [j1]Han Bin Kim, Dong Sam Ha, Takeshi Takahashi, Takahiro J. Yamaguchi:
A new approach to built-in self-testable datapath synthesis based on integer linear programming. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 594-605 (2000) - [c6]Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe:
Jitter measurements of a PowerPCTM microprocessor using an analytic signal method. ITC 2000: 955-964 - [c5]Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Toshifumi Watanabe, Tadahiro Ohmi:
Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method. VTS 2000: 395-402
1990 – 1999
- 1998
- [c4]Masahiro Ishida, Dong Sam Ha, Takahiro J. Yamaguchi:
COMPACT: A Hybrid Method for Compressing Test Data. VTS 1998: 62-69 - 1997
- [c3]Takahiro J. Yamaguchi:
Static Testing of ADCs Using Wavelet Transforms. Asian Test Symposium 1997: 188-193 - [c2]Takahiro J. Yamaguchi, Masahiro Ishida, Marco Tilgner, Dong Sam Ha:
An Efficient Method for Compressing Test Data. ITC 1997: 79-88 - [c1]Takahiro J. Yamaguchi, Mani Soma:
Dynamic Testing of ADCs Using Wavelet Transforms. ITC 1997: 379-388
Coauthor Index
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