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Marie-Lise Flottes
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2020 – today
- 2024
- [j30]Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini:
Utilizing layout effects for analog logic locking. J. Cryptogr. Eng. 14(2): 311-324 (2024) - [c103]Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel:
A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. DATE 2024: 1-6 - [c102]Nassim Riadi
, Florent Bruguier, Pascal Benoit, Sophie Dupuis, Marie-Lise Flottes:
Power Analysis Attack Against post-SAT Logic Locking schemes. ETS 2024: 1-6 - [c101]Sophie Dupuis, Nassim Riadi
Logic Locking: Exploration of a new key-gate based on tristate logic. LATS 2024: 1-6 - [i7]Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini:
Utilizing Layout Effects for Analog Logic Locking. CoRR abs/2401.06508 (2024) - 2023
- [j29]Levent Aksoy
Hybrid Protection of Digital FIR Filters. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 812-825 (2023) - [c100]Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel:
Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. ETS 2023: 1-4 - [c99]Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini:
Resynthesis-based Attacks Against Logic Locking. ISQED 2023: 1-8 - [i6]Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini:
Resynthesis-based Attacks Against Logic Locking. CoRR abs/2301.04400 (2023) - [i5]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini:
Hybrid Protection of Digital FIR Filters. CoRR abs/2301.11115 (2023) - 2022
- [c98]Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini:
Leveraging Layout-based Effects for Locking Analog ICs. ASHES@CCS 2022: 5-13 - [c97]S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing. ETS 2022: 1-4 - [i4]Muayad J. Aljafar
Leveraging Layout-based Effects for Locking Analog ICs. CoRR abs/2209.01856 (2022) - 2021
- [c96]Lila Ammoura, Marie-Lise Flottes, Patrick Girard
Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. DTIS 2021: 1-4 - [c95]S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices. ETS 2021: 1-4 - [c94]Levent Aksoy
High-level Intellectual Property Obfuscation via Decoy Constants. IOLTS 2021: 1-7 - [c93]Quang-Linh Nguyen, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
On Preventing SAT Attack with Decoy Key-Inputs. ISVLSI 2021: 114-119 - [i3]Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini:
High-level Intellectual Property Obfuscation via Decoy Constants. CoRR abs/2105.06122 (2021) - 2020
- [c92]Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS 2020: 1-4 - [c91]Quang-Linh Nguyen, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
A Secure Scan Controller for Protecting Logic Locking. IOLTS 2020: 1-6
2010 – 2019
- 2019
- [j28]Emanuele Valea
A Survey on Security Threats and Countermeasures in IEEE Test Standards. IEEE Des. Test 36(3): 95-116 (2019) - [j27]Sophie Dupuis
Logic Locking: A Survey of Proposed Methods and Evaluation Metrics. J. Electron. Test. 35(3): 273-291 (2019) - [j26]Emanuele Valea
Stream vs block ciphers for scan encryption. Microelectron. J. 86: 65-76 (2019) - [j25]Mathieu Da Silva
Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 538-550 (2019) - [c90]Emanuele Valea
Encryption-Based Secure JTAG. DDECS 2019: 1-6 - [c89]Emanuele Valea
Providing Confidentiality and Integrity in Ultra Low Power IoT Devices. DTIS 2019: 1-6 - [c88]Marc Merandat, Vincent Reynaud, Emanuele Valea
A Comprehensive Approach to a Trusted Test Infrastructure. IVSW 2019: 43-48 - [i2]Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
SECCS: SECure Context Saving for IoT Devices. CoRR abs/1903.04314 (2019) - 2018
- [j24]Sophie Dupuis
Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead. IEEE Des. Test 35(2): 73-90 (2018) - [j23]Raphael Andreoni Camponogara Viera
Assessing body built-in current sensors for detection of multiple transient faults. Microelectron. Reliab. 88-90: 128-134 (2018) - [c87]Emanuele Valea
SI ECCS: SECure context saving for IoT devices. DTIS 2018: 1-2 - [c86]Jean-Max Dutertre
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. FDTC 2018: 1-6 - [c85]Jean-Max Dutertre
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS 2018: 214-219 - [c84]Mathieu Da Silva, Emanuele Valea
A New Secure Stream Cipher for Scan Chain Encryption. IVSW 2018: 68-73 - [c83]Mathieu Da Silva, Emanuele Valea
Encryption of test data: which cipher is better? PRIME 2018: 85-88 - 2017
- [c82]Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo:
Scan chain encryption for the test, diagnosis and debug of secure circuits. ETS 2017: 1-6 - [c81]Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Experimentations on scan chain encryption with PRESENT. IVSW 2017: 45-50 - [c80]Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
Hacking the Control Flow error detection mechanism. IVSW 2017: 51-56 - 2016
- [j22]Stephan De Castro, Jean-Max Dutertre
Frontside Versus Backside Laser Injection: A Comparative Study. ACM J. Emerg. Technol. Comput. Syst. 13(1): 6:1-6:15 (2016) - [c79]Papa-Sidi Ba, Sophie Dupuis, Palanichamy Manikandan
Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. ISVLSI 2016: 254-259 - [c78]Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Using outliers to detect stealthy hardware trojan triggering? IVSW 2016: 1-6 - 2015
- [c77]Sophie Dupuis, Papa-Sidi Ba, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
New testing procedure for finding insertion sites of stealthy hardware trojans. DATE 2015: 776-781 - [c76]Marie-Lise Flottes, Sophie Dupuis, Papa-Sidi Ba, Bruno Rouzeyre:
On the limitations of logic testing for detecting Hardware Trojans Horses. DTIS 2015: 1-5 - [c75]Papa-Sidi Ba, Palanichamy Manikandan
Hardware Trojan prevention using layout-level design approach. ECCTD 2015: 1-4 - [c74]Marie-Lise Flottes, Joao Azevedo, Giorgio Di Natale, Bruno Rouzeyre:
Session-less based thermal-aware 3D-SIC test scheduling. ETS 2015: 1-2 - [c73]Stephan De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Max Dutertre
Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits. ISVLSI 2015: 362-367 - [c72]Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel:
3D DFT Challenges and Solutions. ISVLSI 2015: 603-608 - 2014
- [j21]Jean-Max Dutertre
Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectron. Reliab. 54(9-10): 2289-2294 (2014) - [j20]Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
Test Versus Security: Past and Present. IEEE Trans. Emerg. Top. Comput. 2(1): 50-62 (2014) - [j19]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 947-951 (2014) - [c71]Jean-Max Dutertre
Laser attacks on integrated circuits: From CMOS to FD-SOI. DTIS 2014: 1-6 - [c70]Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Guillaume Hubert
Layout-aware laser fault injection simulation and modeling: From physical level to gate level. DTIS 2014: 1-6 - [c69]Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Customized cell detector for laser-induced-fault detection. IOLTS 2014: 37-42 - [c68]Sophie Dupuis, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans. IOLTS 2014: 49-54 - [c67]Yassine Fkih, Pascal Vivet
2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI 2014: 386-391 - [c66]Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou
Laser-induced fault effects in security-dedicated circuits. VLSI-SoC 2014: 1-6 - [c65]Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre
Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC (Selected Papers) 2014: 220-240 - [c64]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche:
Built-in self-test for manufacturing TSV defects before bonding. VTS 2014: 1-6 - 2013
- [j18]Amitabh Das, Jean DaRolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
Secure JTAG Implementation Using Schnorr Protocol. J. Electron. Test. 29(2): 193-209 (2013) - [j17]Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre:
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. J. Electron. Test. 29(3): 331-340 (2013) - [j16]Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. Inf. Secur. J. A Glob. Perspect. 22(5-6): 226-236 (2013) - [j15]Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Multilevel Ionizing-Induced Transient Fault Simulator. Inf. Secur. J. A Glob. Perspect. 22(5-6): 251-264 (2013) - [j14]Jean-Max Dutertre
Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectron. Reliab. 53(9-11): 1320-1324 (2013) - [j13]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A novel differential scan attack on advanced DFT structures. ACM Trans. Design Autom. Electr. Syst. 18(4): 58:1-58:22 (2013) - [c63]Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Laser-Induced Fault Simulation. DSD 2013: 609-614 - [c62]Rodrigo Possamai Bastos, Frank Sill Torres
A bulk built-in sensor for detection of fault attacks. HOST 2013: 51-54 - [c61]Hakim Zimouche, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A BIST method for TSVs pre-bond test. IDT 2013: 1-6 - [c60]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A smart test controller for scan chains in secure circuits. IOLTS 2013: 228-229 - [c59]Yassine Fkih, Pascal Vivet
A 3D IC BIST for pre-bond test of TSVs using ring oscillators. NEWCAS 2013: 1-4 - [c58]Rodrigo Possamai Bastos, Frank Sill Torres
A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS 2013: 157-163 - 2012
- [j12]Jean DaRolt, Amitabh Das, Santosh Ghosh, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
Scan attacks on side-channel and fault attack resistant public-key implementations. J. Cryptogr. Eng. 2(4): 207-219 (2012) - [j11]Rodrigo Possamai Bastos, Frank Sill Torres
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. Microelectron. Reliab. 52(9-10): 1781-1786 (2012) - [c57]Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
A New Scan Attack on RSA in Presence of Industrial Countermeasures. COSADE 2012: 89-104 - [c56]Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures. DFT 2012: 43-48 - [c55]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
On-chip test comparison for protecting confidential data in secure ICs. ETS 2012: 1 - [c54]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Are advanced DfT structures sufficient for preventing scan-attacks? VTS 2012: 246-251 - [p1]Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
On Countermeasures Against Fault Attacks on the Advanced Encryption Standard. Fault Analysis in Cryptography 2012: 89-108 - 2011
- [c53]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Réal:
Power consumption traces realignment to improve differential power analysis. DDECS 2011: 201-206 - [c52]Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. DFT 2011: 302-308 - [c51]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Scan Attacks and Countermeasures in Presence of Scan Response Compactors. ETS 2011: 19-24 - [c50]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
New security threats against chips containing scan chain structures. HOST 2011: 110 - [c49]Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Timing issues for an efficient use of concurrent error detection codes. LATW 2011: 1-6 - 2010
- [j10]Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
Self-Test Techniques for Crypto-Devices. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 329-333 (2010) - [c48]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Ensuring high testability without degrading security: Embedded tutorial on "test and security". DDECS 2010: 6 - [c47]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA 2010: 256-261 - [c46]Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. ETS 2010: 252 - [c45]Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Evaluation of concurrent error detection techniques on the advanced encryption standard. IOLTS 2010: 223-228
2000 – 2009
- 2009
- [j9]Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. J. Electron. Test. 25(4-5): 269-278 (2009) - [j8]Beatrice Pradarelli, Laurent Latorre, Marie-Lise Flottes, Yves Bertrand, Pascal Nouet
Remote Labs for Industrial IC Testing. IEEE Trans. Learn. Technol. 2(4): 304-311 (2009) - [c44]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Execution time reduction of Differential Power Analysis experiments. LATW 2009: 1-5 - 2008
- [c43]M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. DELTA 2008: 314-321 - [c42]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
An Integrated Validation Environment for Differential Power Analysis. DELTA 2008: 527-532 - [c41]Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
A Reliable Architecture for the Advanced Encryption Standard. ETS 2008: 13-18 - [c40]Julien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre:
Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI 2008: 139-144 - [c39]Ziad Noun, Philippe Cauvet, Marie-Lise Flottes, David Andreu
Wireless Test Structure for Integrated Systems. ITC 2008: 1 - 2007
- [j7]David Hély
Securing Scan Control in Crypto Chips. J. Electron. Test. 23(5): 457-464 (2007) - [c38]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A Novel Parity Bit Scheme for SBox in AES Circuits. DDECS 2007: 267-271 - [c37]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS 2007: 57-62 - [c36]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A Dependable Parallel Architecture for SBoxes. ReCoSoC 2007: 132-137 - [c35]Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre:
Compression-based SoC Test Infrastructures. VLSI-SoC (Selected Papers) 2007: 1-15 - [c34]Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre:
Test data compression and TAM design. VLSI-SoC 2007: 178-183 - [i1]Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre:
Mutation Sampling Technique for the Generation of Structural Test Data. CoRR abs/0710.4802 (2007) - 2006
- [c33]David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre:
A secure scan design methodology. DATE 2006: 1177-1178 - [c32]Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre:
Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA 2006: 295-300 - [c31]David Hély
Secure Scan Techniques: A Comparison. IOLTS 2006: 119-124 - [c30]David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre:
Scan Pattern Watermarking. LATW 2006: 63-67 - 2005
- [c29]Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre:
Mutation Sampling Technique for the Generation of Structural Test Data. DATE 2005: 1022-1023 - [c28]David Hély
Test control for secure scan designs. ETS 2005: 190-195 - [c27]Laurent Latorre, Yves Bertrand, Michel Robert, Marie-Lise Flottes:
Test Engineering Education in Europe - The CRTC experience through the EuNICE-Test project. EDUTECH 2005: 63-77 - 2004
- [c26]Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre:
An Arithmetic Structure for Test Data Horizontal Compression. DATE 2004: 428-435 - [c25]Marie-Lise Flottes, Yves Bertrand, Luz Balado, Emili Lupon
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. DELTA 2004: 135-139 - [c24]Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre:
On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA 2004: 275-280 - [c23]Ludovic A. Krundel
User-constrained test architecture design for modular SOC testing. ETS 2004: 80-85 - [c22]David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell:
Scan Design and Secure Chip. IOLTS 2004: 219-226 - 2003
- [j6]Marie-Lise Flottes, Christian Landrault, A. Petitqueux:
A Unified DFT Approach for BIST and External Test. J. Electron. Test. 19(1): 49-60 (2003) - [c21]Julien Pouget, Erik Larsson
An efficient approach to SoC wrapper design, TAM configuration and test scheduling. ETW 2003: 51-56 - [c20]Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo
Test Engineering Education in Europe: the EuNICE-Test Project. MSE 2003: 85-86 - 2002
- [j5]Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe:
Improving Datapath Testability by Modifying Controller Specification. VLSI Design 15(2): 491-498 (2002) - [c19]Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre:
A Heuristic for Test Scheduling at System Level. DATE 2002: 1124 - [c18]Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard
European Network for Test Education. DELTA 2002: 230-234 - [c17]Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre:
A simple and effective compression scheme for test pins reduction. HLDVT 2002: 165-168 - [e1]Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes:
SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France. IFIP Conference Proceedings 218, Kluwer 2002, ISBN 1-4020-7148-5 [contents] - 2001
- [j4]David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis. J. Electron. Test. 17(3-4): 331-339 (2001) - [c16]Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre:
Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. VLSI-SOC 2001: 401-412 - 2000
- [c15]Marie-Lise Flottes, Christian Landrault, A. Petitqueux:
Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Asian Test Symposium 2000: 404- - [c14]David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
A method for trading off test time, area and fault coverage in datapath BIST synthesis. ETW 2000: 133-139 - [c13]Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe:
A controller resynthesis based method for improving datapath testability. ISCAS 2000: 347-350 - [c12]David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
BISTing data paths at behavioral level. ITC 2000: 672-680
1990 – 1999
- 1999
- [j3]David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
BISTing Datapaths under Heterogeneous Test Schemes. J. Electron. Test. 14(1-2): 115-123 (1999) - [c11]Marie-Lise Flottes, Christian Landrault, A. Petitqueux:
Partial set for flip-flops based on state requirement for non-scan BIST scheme. ETW 1999: 104-109 - [c10]Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival:
A Successful Distance-Learning Experience for IC Test Education. MSE 1999: 20-21 - 1998
- [c9]Marie-Lise Flottes, R. Pires, Bruno Rouzeyre:
Alleviating DFT Cost Using Testability Driven HLS. Asian Test Symposium 1998: 46-51 - [c8]Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe:
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. DATE 1998: 921-922 - [c7]Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe:
Low Cost Partial Scan Design: A High Level Synthesis Approach. VTS 1998: 332-340 - 1997
- [j2]Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
Improving Testability of Non-Scan Designs during Behavioral Synthesis. J. Electron. Test. 11(1): 29-42 (1997) - [c6]Marie-Lise Flottes, R. Pires, Bruno Rouzeyre:
Analyzing testability from behavioral to RT level. ED&TC 1997: 158-165 - 1995
- [c5]Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
High-level synthesis for easy testability. ED&TC 1995: 198-206 - [c4]Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre:
Is High-Level Test Synthesis Just Design for Test? ITC 1995: 294 - 1994
- [c3]Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
Automatic Synthesis of BISTed Data Paths From High Level Specification. EDAC-ETC-EUROASIC 1994: 591-598 - 1992
- [c2]Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
A New Reliable Method for Delay-Fault Diagnosis. VLSI Design 1992: 12-16 - 1991
- [j1]Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch:
Fault modeling and fault equivalence in CMOS technology. J. Electron. Test. 2(3): 229-241 (1991) - 1990
- [c1]Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch:
Fault modelling and fault equivalence in CMOS technology. EURO-DAC 1990: 407-412
Coauthor Index
[j28] [j26] [j25] [c90] [c89] [c88] [i2] [j24] [j23] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [j22] [c79] [c78] [c77] [c75] [c74] [c73] [c72] [j21] [j20] [j19] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [j18] [j17] [j16] [j15] [j14] [j13] [c63] [c62] [c61] [c60] [c59] [c58] [j12] [j11] [c57] [c56] [c55] [c54] [p1] [c53] [c52] [c51] [c50] [c49] [j10] [c48] [c47] [c46] [c45] [j9] [c44] [c42] [c41] [c38] [c37] [c36]
Samuel Nascimento Pagliarini
aka: Samuel Pagliarini
aka: Samuel Pagliarini
[c97] [c95] [c93] [c92] [c91] [j28] [j26] [j25] [c90] [c89] [c88] [i2] [j24] [j23] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [j22] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [j21] [j20] [j19] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [j18] [j17] [j16] [j15] [j14] [j13] [c63] [c62] [c61] [c60] [c59] [c58] [j12] [j11] [c57] [c56] [c55] [c54] [p1] [c53] [c52] [c51] [c50] [c49] [j10] [c48] [c47] [c46] [c45] [j9] [c44] [c43] [c42] [c41] [c40] [j7] [c38] [c37] [c36] [c35] [c34] [i1] [c33] [c32] [c31] [c30] [c29] [c28] [c26] [c24] [c23] [c22] [c21] [j5] [c19] [c17] [e1] [j4] [c16] [c14] [c13] [c12] [j3] [c9] [c8] [c7] [j2] [c6] [c5] [c4] [c3]
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