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ICCAD 1994: San Jose, California, USA
- Jochen A. G. Jess, Richard L. Rudell:
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994. IEEE Computer Society / ACM 1994, ISBN 0-89791-690-5 - Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Perturb and simplify: multi-level boolean network optimizer. 2-5 - Wolfgang Kunz, Prem R. Menon:
Multi-level logic optimization by implication analysis. 6-13 - Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain:
Incremental synthesis. 14-18 - David Karchmer, Jonathan Rose:
Definition and solution of the memory packing problem for field-programmable systems. 20-26 - David J. Kolson, Alexandru Nicolau, Nikil D. Dutt
:
Integrating program transformations in the memory-based synthesis of image and video algorithms. 27-30 - Florin Balasa, Francky Catthoor, Hugo De Man:
Dataflow-driven memory allocation for multi-dimensional signal processing systems. 31-34 - Uwe Gläser, Heinrich Theodor Vierhaus, M. Kley, A. Wiederhold:
Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. 36-39 - Daniel G. Saab, Youssef Saab, Jacob A. Abraham:
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. 40-43 - Giri Devarayanadurg, Mani Soma:
Analytical fault modeling and static test generation for analog ICs. 44-47 - Honghua Yang, D. F. Wong
Efficient network flow based min-cut balanced partitioning. 50-55 - Jason Cong, Wilburt Labio, Narayanan Shivakumar:
Multi-way VLSI circuit partitioning based on dual net representation. 56-62 - Charles J. Alpert, Andrew B. Kahng:
A general framework for vertex orderings, with applications to netlist clustering. 63-67 - Gary D. Hachtel, Mariano Hermida de la Rica, Abelardo Pardo, Massimo Poncino, Fabio Somenzi:
Re-encoding sequential circuits to reduce power dissipation. 70-73 - Mazhar Alidina, José Monteiro
Precomputation-based sequential logic optimization for low power. 74-81 - Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain:
Low power state assignment targeting two-and multi-level logic implementations. 82-87 - Miodrag Potkonjak, Jan M. Rabaey:
Algorithm selection: a quantitative computation-intensive optimization approach. 90-95 - Jörg Henkel, Rolf Ernst, Ulrich Holtmann, Thomas Benner:
Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis. 96-100 - Bill Lin, Steven Vercauteren:
Synthesis of concurrent system interface modules with automatic protocol conversion generation. 101-108 - Sybille Hellebrand, Hans-Joachim Wunderlich:
An efficient procedure for the synthesis of fast self-testable controller structures. 110-116 - Sanjay Gupta, Janusz Rajski, Jerzy Tyszer:
Test pattern generation based on arithmetic operations. 117-124 - Chen-Huan Chiang, Sandeep K. Gupta:
Random pattern testable logic synthesis. 125-128 - Anmol Mathur, C. L. Liu:
Compression-relaxation: a new approach to performance driven placement for regular architectures. 130-136 - Wern-Jieh Sun, Carl Sechen:
A loosely coupled parallel algorithm for standard cell placement. 137-144 - Weitong Chuang, Ibrahim N. Hajj:
Delay and area optimization for compact placement by gate resizing and relocation. 145-148 - Hannah Honghua Yang, D. F. Wong
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. 150-155 - Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. 156-163 - Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin:
Universal logic gate for FPGA design. 164-168 - Hsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski:
Condition graphs for high-quality behavioral synthesis. 170-174 - Claudionor José Nunes Coelho Jr., Giovanni De Micheli:
Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints. 175-181 - Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt
Comprehensive lower bound estimation from behavioral descriptions. 182-187 - Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee:
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. 190-194 - Meng-Lin Yu, Bryan D. Ackland:
VLSI timing simulation with selective dynamic regionization. 195-199 - Syed A. Aftab, M. A. Styblinski:
A new efficient approach to statistical delay modeling of CMOS digital combinational circuits. 200-203 - Jason Cong, Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization. 206-212 - Andrew B. Kahng, Chung-Wen Albert Tsao:
Low-cost single-layer clock trees with exact zero Elmore delay skew. 213-218 - Gustavo E. Téllez, Majid Sarrafzadeh:
Clock period constrained minimal buffer insertion in clock trees. 219-223 - Narendra V. Shenoy, Richard L. Rudell:
Efficient implementation of retiming. 226-233 - Tolga Soyata, Eby G. Friedman:
Retiming with non-zero clock skew, variable register, and interconnect delay. 234-241 - Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann:
Optimal latch mapping and retiming within a tree. 242-245 - Mark H. Linderman, Miriam Leeser:
Simulation of digital circuits in the presence of uncertainty. 248-251 - Wolfgang T. Eisenmann, Helmut E. Graeb:
Fast transient power and noise estimation for VLSI circuits. 252-257 - Peter M. Maurer:
The Inversion Algorithm for digital simulation. 258-261 - Mitiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac:
Unified complete MOSFET model for analysis of digital and analog circuits. 264-267 - Joel R. Phillips, Jacob K. White:
A precorrected-FFT method for capacitance extraction of complicated 3-D structures. 268-271 - Eric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli:
Measurement and modeling of MOS transistor current mismatch in analog IC's. 272-277 - Jae Chung, Chung-Kuan Cheng:
Skew sensitivity minimization of buffered clock tree. 280-283 - Shen Lin, C. K. Wong:
Process-variation-tolerant clock skew minimization. 284-288 - Mitsuho Seki, Kenji Inoue, Kazuo Kato, Kouki Tsurusaki, Shin'ichi Fukasawa, Hitoshi Sasaki, Mutsuhito Aizawa:
A specified delay accomplishing clock router using multiple layers. 289-292 - Radu Marculescu, Diana Marculescu
Switching activity analysis considering spatiotemporal correlations. 294-299 - Tan-Li Chou, Kaushik Roy, Sharat Prasad:
Estimation of circuit activity considering signal correlations and simultaneous switching. 300-303 - Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen:
A cell-based power estimation in CMOS combinational circuits. 304-309 - Smita Bakshi, Daniel D. Gajski:
Design exploration for high-performance pipelines. 312-316 - Yung-Ming Fang, D. F. Wong
Simultaneous functional-unit binding and floorplanning. 317-321 - Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
Module selection and data format conversion for cost-optimal DSP synthesis. 322-329 - Irith Pomeranz, Sudhakar M. Reddy:
On testing delay faults in macro-based combinational circuits. 332-339 - Abhijit Chatterjee, Jacob A. Abraham:
RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults. 340-343 - Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta:
A comprehensive fault macromodel for opamps. 344-348 - Shigetoshi Nakatake, Yoji Kajitani:
Channel-driven global routing with consistent placement (extended abstract). 350-355 - Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
A new global routing algorithm for FPGAs. 356-361 - Yu-Liang Wu, Douglas Chang:
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution. 362-366 - R. Iris Bahar
A symbolic method to reduce power consumption of circuits containing false paths. 368-371 - Sasan Iman, Massoud Pedram:
Multi-level network optimization for low power. 372-377 - Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita:
LP based cell selection with constraints of timing, area, and power consumption. 378-381 - Vivek Tiwari, Sharad Malik
Power analysis of embedded software: a first step towards software power minimization. 384-390 - Ing-Jer Huang, Alvin M. Despain:
Generating instruction sets and microarchitectures from applications. 391-396 - Clifford Liem, Trevor C. May, Pierre G. Paulin:
Register assignment through resource classification for ASIP microcode generation. 397-402 - Roland W. Freund, Peter Feldmann:
Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithm. 404-411 - Haifang Liao, Wayne Wei-Ming Dai:
Capturing time-of-flight delay for transient analysis based on scattering parameter macromodel. 412-417 - Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage:
RC interconnect synthesis-a moment fitting approach. 418-425 - Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato:
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays. 428-431 - Venkat Thanvantri, Sartaj K. Sahni:
Folding a stack of equal width components. 432-435 - Peichen Pan, Weiping Shi, C. L. Liu:
Area minimization for hierarchical floorplans. 436-440 - Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton:
Multi-level synthesis for safe replaceability. 442-449 - Felice Balarin, Alberto L. Sangiovanni-Vincentelli:
Iterative algorithms for formal verification of embedded real-time systems. 450-457 - Gitanjali Swamy, Robert K. Brayton:
Incremental formal design verification. 458-465 - Timothy M. Burks, Karem A. Sakallah:
Optimization of critical paths in circuits with level-sensitive latches. 468-473 - Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess:
Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. 474-480 - How-Rern Lin, TingTing Hwang:
Dynamical identification of critical paths for iterative gate sizing. 481-484 - Salvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois:
Built-in self-test and fault diagnosis of fully differential analogue circuits. 486-490 - Karim Arabi, Bozena Kaminska, Janusz Rzeszut:
A new built-in self-test approach for digital-to-analog and analog-to-digital converters. 491-494 - Georges G. E. Gielen, Zhihua Wang, Willy M. C. Sansen:
Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring. 495-498 - Pieter van der Wolf, K. Olav ten Bosch, Alfred van der Hoeven:
An enhanced flow model for constraint handling in hierarchical multi-view design environments. 500-507 - Bernd Schürmann, Joachim Altmeyer, Martin Schütze:
On modeling top-down VLSI design. 508-515 - Margarida F. Jacome, Stephen W. Director:
A formal basis for design process planning and management. 516-521 - Gert Goossens, Ivo Bolsens, Bill Lin, Francky Catthoor:
Design of heterogeneous ICs for mobile and personal communication systems. 524-531 - Michael A. Schuette, John R. Barr:
Embedded systems design for low energy consumption. 534-540 - Bill Lin, Srinivas Devadas:
Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. 542-549 - Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas:
Performance-driven synthesis of asynchronous controllers. 550-557 - Polly Siegel, Giovanni De Micheli:
Decomposition methods for library binding of speed-independent asynchronous designs. 558-565 - Irith Pomeranz, Sudhakar M. Reddy:
On error correction in macro-based circuits. 568-575 - Vamsi Boppana, W. Kent Fuchs:
Fault dictionary compaction by output sequence removal. 576-579 - Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose:
Automatic test program generation for pipelined processors. 580-583 - Tamal Mukherjee
Synthesis of manufacturable analog circuits. 586-593 - Fernando Medeiro, Francisco V. Fernández, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez:
A statistical optimization-based approach for automated sizing of analog cells. 594-597 - Alper Demir, Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli:
Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations. 598-603 - Xiaolin Liu, Ioannis G. Tollis:
Improving over-the-cell channel routing in standard cell design. 606-609 - Tong Gao, C. L. Liu:
Minimum crosstalk switchbox routing. 610-615 - Desmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli:
Techniques for crosstalk avoidance in the physical design of high-performance digital systems. 616-619 - Pranav Ashar, Matthew Cheong:
Efficient breadth-first manipulation of binary decision diagrams. 622-627 - Shipra Panda, Fabio Somenzi, Bernard Plessier:
Symmetry detection and dynamic variable ordering of decision diagrams. 628-631 - Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton:
A redesign technique for combinational circuits based on gate reconnections. 632-637 - Sujit Dey, Miodrag Potkonjak:
Non-scan design-for-testability of RT-level data paths. 640-645 - Toshinobu Ono:
Selecting partial scan flip-flops for circuit partitioning. 646-650 - Nur A. Touba, Edward J. McCluskey:
Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. 651-654 - Jianfeng Shao, Ramesh Harjani:
Macromodeling of analog circuits for hierarchical circuit design. 656-663 - Qicheng Yu, Carl Sechen:
Approximate symbolic analysis of large analog integrated circuits. 664-671 - Eric Felt, Alberto L. Sangiovanni-Vincentelli:
Testing of analog systems using behavioral models and optimal experimental design techniques. 672-678 - Kai-Yuan Chao, D. F. Wong
Layer assignment for high-performance multi-chip modules. 680-685 - Wei-Liang Lin, Majid Sarrafzadeh, Chak-Kuen Wong:
The reproducing placement problem with applications. 686-689 - Chih-Liang Eric Cheng:
RISA: accurate and efficient placement routability modeling. 690-695 - Chunduri Rama Mohan, Partha Pratim Chakrabarti:
A new approach for factorizing FSM's. 698-701 - Ney Laert Vilar Calazans:
Boolean constrained encoding: a new formulation and a case study. 702-706 - Heinz-Josef Eikerling, Ralf Hunstock, Raul Camposano:
Optimization of hierarchical designs using partitioning and resynthesis. 707-712 - Chen-Pin Kung, Chen-Shang Lin:
HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults. 714-718 - Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel:
Fast timing simulation of transient faults in digital circuits. 719-722 - Jer-Min Jou, Shung-Chih Chen:
A fast and memory-efficient diagnostic fault simulation for sequential circuits. 723-726 - John R. Feehrer, Harry F. Jordan:
Timing uncertainty analysis for time-of-flight systems. 728-735 - Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Provably correct high-level timing analysis without path sensitization. 736-742 - Jin-Fuw Lee, Donald T. Tang, C. K. Wong:
A timing analysis algorithm for circuits with level-sensitive latches. 743-748 - Naresh Sehgal, C. Y. Roger Chen, John M. Acken:
An object-oriented cell library manager. 750-753 - Joachim Altmeyer, Stefan Ohnsorge, Bernd Schürmann:
Reuse of design objects in CAD frameworks. 754-761 - Olav Schettler, Susanne Heymann:
Towards support for design description languages in EDA framework. 762-767
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