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Heinrich Theodor Vierhaus
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- affiliation: Brandenburg University of Technology, Cottbus, Germany
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2020 – today
- 2020
- [c94]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda
, Milos Krstic
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE 2020: 388-393
2010 – 2019
- 2019
- [i1]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR abs/1912.01561 (2019) - 2018
- [c93]Farnoosh Hosseinzadeh, Petr Pfeifer, Heinrich Theodor Vierhaus:
Optimal Dependability and Fine Granular Error Resilience Methodology for Reconfigurable Systems. DSD 2018: 206-213 - [c92]Heinrich Theodor Vierhaus, Maksim Jenihhin
RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality. EWME 2018: 45-50 - [c91]Heinrich Theodor Vierhaus:
Migrating Electronic Systems from Fault Tolerant Computing to Error Resilience. SPA 2018: 13 - 2017
- [j16]Christian Gleichner, Heinrich Theodor Vierhaus:
Test and Diagnosis of Automotive Embedded Processors via High-Speed Standard Interfaces. J. Circuits Syst. Comput. 26(8): 1740006:1-1740006:17 (2017) - [c90]Davide Dicorato, Petr Pfeifer, Heinrich Theodor Vierhaus:
Fault detection and self repair in Hsiao-code FEC circuits. DDECS 2017: 42-47 - [c89]Petr Pfeifer, Farnoosh Hosseinzadeh, Heinrich Theodor Vierhaus:
On comparison of robust configurable FPGA encoders for dependable industrial communication systems. IOLTS 2017: 199-200 - [c88]Stefan Scharoba
Fast power overhead prediction for hardware redundancy-based fault tolerance. IOLTS 2017: 265-270 - [c87]Petr Pfeifer, Heinrich Theodor Vierhaus:
Forward error correction in wireless communication systems for industrial applications. SPA 2017: 14 - [c86]Farnoosh Hosseinzadeh, Petr Pfeifer, Heinrich Theodor Vierhaus:
The coarse and fine granular fault tolerance techniques in FPGA-based processors. SPA 2017: 116-120 - 2016
- [j15]Roberto Urban, Heinrich Theodor Vierhaus, Mario Schölzel, Enrico Altmann, Horst Seelig:
Non-Cyclic Design Space Exploration for ASIPs - Compiler-Centered Microprocessor Design (CoMet). J. Circuits Syst. Comput. 25(3): 1640012:1-1640012:16 (2016) - [c85]Christian Gleichner, Heinrich Theodor Vierhaus:
Test of automotive embedded processors with high diagnostic resolution. DDECS 2016: 113-118 - [c84]Stefan Scharoba
An Interactive Design Space Exploration Tool for Dependable Integrated Circuits. DSD 2016: 714-717 - [c83]Mario Schölzel, Tobias Koal, Sebastian Müller, Stefan Scharoba
A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors. LATS 2016: 33-38 - [c82]Petr Pfeifer
Iterative error correction with double/triple error detection. SPA 2016: 14-19 - 2015
- [c81]Tobias Koal, Heinrich Theodor Vierhaus:
Redundancy evaluation process of processor components for permanent fault compensation. AHS 2015: 1-6 - [c80]Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus, Enrico Altmann, Horst Seelig:
Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP. DDECS 2015: 17-22 - [c79]Tobias Koal, Stefan Scharoba
Combining Correction of Delay Faults and Transient Faults. DDECS 2015: 99-102 - [c78]Mario Schölzel, Heinrich Theodor Vierhaus:
Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen. GI-Jahrestagung 2015: 1377 - [c77]Christian Gleichner, Heinrich Theodor Vierhaus:
Test eingebetteter Prozessoren im Zielsystem mit hoher diagnostischer Auflösung. GI-Jahrestagung 2015: 1399-1413 - [c76]Davide Dicorato, Heinrich Theodor Vierhaus:
Detection and Correction of Logic Errors Using Extra Time Slots. GI-Jahrestagung 2015: 1431-1443 - [c75]Ansgar Scherp, Steffen Becker, Heinrich Theodor Vierhaus:
Doktorandenprogramm der INFORMATIK 2015. GI-Jahrestagung 2015: 1737-1738 - [c74]Raimund Ubar
Multiple fault testing in systems-on-chip with high-level decision diagrams. IDT 2015: 66-71 - [c73]Sebastian Müller, Tobias Koal, Stefan Scharoba
A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems. LATS 2015: 1-6 - [c72]Heinrich Theodor Vierhaus:
Error resilience in nano-electronic digital circuits and systems. SPA 2015: 9 - [e4]Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus:
18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-6779-7 [contents] - 2014
- [c71]Tobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus:
Combining fault tolerance and self repair at minimum cost in power and hardware. DDECS 2014: 153-158 - [c70]Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus:
Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults. DFT 2014: 27-32 - [c69]Davide Sabena, Luca Sterpone
Reconfigurable high performance architectures: How much are they ready for safety-critical applications? ETS 2014: 1-8 - [c68]Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus:
Systematic generation of diagnostic software-based self-test routines for processor components. ETS 2014: 1-6 - [c67]Heinrich Theodor Vierhaus, Mario Schölzel, Jaan Raik
Advanced technical education in the age of cyber physical systems. EWME 2014: 193-198 - [c66]Sebastian Müller, Tobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus:
Timing for virtual TMR in logic circuits. IOLTS 2014: 190-193 - [c65]Roberto Urban, Kai Lehniger, Maximilian Heyne, Mario Schölzel, Heinrich Theodor Vierhaus:
Vergleich der Beschreibung und Simulation einer Befehlssatzarchitektur in LISA und CoMet. MBMV 2014: 101-111 - 2013
- [c64]Petr Pfeifer
On performance estimation of a scalable VLIW soft-core in XILINX FPGAs. DDECS 2013: 181-186 - [c63]Tobias Koal, Markus Ulbricht, Piet Engelke, Heinrich Theodor Vierhaus:
On the feasibility of combining on-line-test and self repair for logic circuits. DDECS 2013: 187-192 - [c62]Tobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus:
Virtual TMR Schemes Combining Fault Tolerance and Self Repair. DSD 2013: 235-242 - [c61]Mario Schölzel, Tobias Koal, Stephanie Roder, Heinrich Theodor Vierhaus:
Towards an automatic generation of diagnostic in-field SBST for processor components. LATW 2013: 1-6 - [c60]Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus:
Ein konfigurierbarer Zwischencodesimulator zum compilerzentrierten Mikroprozessorentwurf. MBMV 2013: 13-24 - [c59]Sebastian Müller, Mario Schölzel, Heinrich Theodor Vierhaus:
Towards a Graceful Degradable Multicore-System by Hierarchical Handling of Hard Errors. PDP 2013: 302-309 - 2012
- [c58]Sebastian Müller, Mario Schölzel, Heinrich Theodor Vierhaus:
Hierarchical Self-repair in Heterogeneous Multi-core Systems by Means of a Software-based Reconfiguration. ARCS Workshops 2012: 251-262 - [c57]Tobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus:
Combining on-line fault detection and logic self repair. DDECS 2012: 288-293 - [c56]Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus:
An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores. DDECS 2012: 312-317 - [c55]Markus Ulbricht, Heinrich Theodor Vierhaus, Tobias Koal:
Activity Migration in M-of-N-Systems by Means of Load-Balancing. DSD 2012: 258-263 - [c54]Christian Gleichner, Heinrich Theodor Vierhaus, Piet Engelke:
Scan Based Tests via Standard Interfaces. DSD 2012: 844-851 - [e3]Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin:
IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012. IEEE 2012, ISBN 978-1-4673-1187-8 [contents] - 2011
- [c53]Markus Ulbricht, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus:
A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. DDECS 2011: 143-146 - [c52]Tobias Koal, Heinrich Theodor Vierhaus:
Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair. DDECS 2011: 219-224 - [c51]Tobias Koal, Daniel Scheit, Mario Schölzel, Heinrich Theodor Vierhaus:
On the Feasibility of Built-In Self Repair for Logic Circuits. DFT 2011: 316-324 - [e2]Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011. IEEE Computer Society 2011, ISBN 978-1-4244-9755-3 [contents] - 2010
- [c50]Tobias Koal, Heinrich Theodor Vierhaus:
A software-based self-test and hardware reconfiguration solution for VLIW processors. DDECS 2010: 40-43 - [c49]Tobias Koal, Heinrich Theodor Vierhaus:
Combining de-stressing and self repair for long-term dependable systems. DDECS 2010: 99-104 - [c48]René Kothe, Heinrich Theodor Vierhaus:
Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. DSD 2010: 283-290 - [e1]Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-6612-2 [contents]
2000 – 2009
- 2009
- [c47]Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus:
A scheme of logic self repair including local interconnects. DDECS 2009: 8-11 - [c46]Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus:
Reliability Estimation Process. DSD 2009: 221-224 - [c45]Tobias Koal, Heinrich Theodor Vierhaus, Daniel Scheit:
A Concept for Logic Self Repair. DSD 2009: 621-624 - 2008
- [j14]René Kothe, Heinrich Theodor Vierhaus:
A Scan Controller Concept for Low Power Scan Tests. J. Low Power Electron. 4(3): 420-428 (2008) - [j13]Silvio Misera, Heinrich Theodor Vierhaus, André Sieber:
Simulated fault injections and their acceleration in SystemC. Microprocess. Microsystems 32(5-6): 270-278 (2008) - [c44]Heinrich Theodor Vierhaus, René Kothe:
Embedded Diagnostic Logic Test Exploiting Regularity. DSD 2008: 873-879 - [c43]Tobias Koal, Heinrich Theodor Vierhaus:
Basic Architecture for Logic Self Repair. IOLTS 2008: 177-178 - 2007
- [c42]René Kothe, Heinrich Theodor Vierhaus:
Flip-Flops and Scan-Path Elements for Nanoelectronics. DDECS 2007: 307-312 - [c41]Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera:
Timing- / Power-Optimization for Digital Logic Based on Standard Cells. DSD 2007: 303-306 - [c40]Silvio Misera, Heinrich Theodor Vierhaus, André Sieber:
Fault Injection Techniques and their Accelerated Simulation in SystemC. DSD 2007: 587-595 - [c39]R. Frost, D. Rudolph, Christian Galke, René Kothe, Heinrich Theodor Vierhaus:
A Configurable Modular Test Processor and Scan Controller Architecture. IOLTS 2007: 277-284 - 2006
- [c38]Christian Galke, René Kothe, Heinrich Theodor Vierhaus:
Logic Self Repair. ARCS Workshops 2006: 36-44 - [c37]Udo Krautz, Matthias Pflanz, Christian Jacobi, Hans-Werner Tast, Kai Weber, Heinrich Theodor Vierhaus:
Evaluating coverage of error detection logic for soft errors using formal methods. DATE 2006: 176-181 - [c36]René Kothe, Christian Galke, Sabine Schultke, Henry Fröschke, Steffen Gaede, Heinrich Theodor Vierhaus:
Hardware/Software Based Hierarchical Self Test for SoCs. DDECS 2006: 159-160 - [c35]René Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube:
Embedded Self Repair by Transistor and Gate Level Reconfiguration. DDECS 2006: 210-215 - [c34]Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber:
A Mixed Language Fault Simulation of VHDL and SystemC. DSD 2006: 275-279 - [c33]Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus:
Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. DSD 2006: 433-438 - [c32]Christian Galke, René Kothe, Sabine Schultke, K. Winkler, Jeanette Honko, Heinrich Theodor Vierhaus:
Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. IOLTS 2006: 181-182 - [c31]S. Habermann, René Kothe, Heinrich Theodor Vierhaus:
Built-in Self Repair by Reconfiguration of FPGAs. IOLTS 2006: 187-188 - [c30]Axel Vick, Helmut Rossmann, Heinrich Theodor Vierhaus:
Timing-/Power-getriebener Layout-Entwurf für Zellen-basierte Digitalschaltungen. MBMV 2006: 61-68 - 2005
- [c29]Heinrich Theodor Vierhaus, Helmut Rossmann:
Power-/Timing - Optimierung für Zellen-basierte Digitalschaltungen in Submikron-Technologien. GI Jahrestagung (1) 2005: 339-343 - [c28]René Kothe, Christian Galke, Heinrich Theodor Vierhaus:
A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. IOLTS 2005: 241-246 - [c27]Marcin Gomulkiewicz, Miroslaw Kutylowski, Heinrich Theodor Vierhaus, Pawel Wlaz:
Synchronization Fault Cryptanalysis for Breaking A5/1. WEA 2005: 415-427 - 2004
- [c26]Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus:
A Hierarchical Self Test Scheme for SoCs. IOLTS 2004: 37-44 - [c25]Silvio Misera, Heinrich Theodor Vierhaus:
FIT - A Parallel Hierarchical Fault Simulation Environment. PARELEC 2004: 289-294 - 2003
- [j12]Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus:
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check. J. Electron. Test. 19(5): 501-510 (2003) - [c24]Matthias Pflanz, Heinrich Theodor Vierhaus:
Control Signal Protection For High Performance Processors. IOLTS 2003: 173- - [c23]Christian Galke, Marcus Grabow, Heinrich Theodor Vierhaus:
Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip. IOLTS 2003: 183- - 2002
- [c22]Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus:
A Test Processor Concept for Systems-on-a-Chip. ICCD 2002: 210- - [c21]Matthias Pflanz, Karsten Walther, Christian Galke, Heinrich Theodor Vierhaus:
On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check. IOLTW 2002: 69-73 - [c20]Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus:
On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures. IOLTW 2002: 178 - 2001
- [j11]Matthias Pflanz, Heinrich Theodor Vierhaus:
Online Check and Recovery Techniques for Dependable Embedded Processors. IEEE Micro 21(5): 24-40 (2001) - [c19]C. Rousselle, Matthias Pflanz, A. Behling, T. Mohaupt, Heinrich Theodor Vierhaus:
A register-transfer-level fault simulator for permanent and transient faults in embedded processors. DATE 2001: 811 - [c18]Matthias Pflanz, Karsten Walther, Heinrich Theodor Vierhaus:
On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity. IOLTW 2001: 51-53 - 2000
- [c17]Matthias Pflanz, Christian Galke, Heinrich Theodor Vierhaus:
A new method for on-line state machine observation for embedded microprocessors. HLDVT 2000: 34-39
1990 – 1999
- 1999
- [j10]Fulvio Corno
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 191-202 (1999) - [c16]Matthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch:
An efficient on-line-test and back-up scheme for embedded processors. ITC 1999: 964-972 - 1998
- [j9]Matthias Pflanz, Heinrich Theodor Vierhaus:
Generating reliable embedded processors. IEEE Micro 18(5): 33-41 (1998) - 1997
- [j8]Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano:
Partitioning and analysis of static digital CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1292-1310 (1997) - [c15]H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus:
An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation. Great Lakes Symposium on VLSI 1997: 112-117 - [c14]H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus:
A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits. PARCO 1997: 549-556 - 1996
- [j7]Uwe Gläser, Heinrich Theodor Vierhaus:
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4): 410-423 (1996) - [c13]Jörg Wilberg, A. Kuth, Raul Camposano, Wolfgang Rosenstiel, Heinrich Theodor Vierhaus:
A Design Exploration Environment. Great Lakes Symposium on VLSI 1996: 77-80 - [c12]H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus:
Automatic Test Pattern Generation with Optimal Load Balancing. PVM 1996: 205-212 - 1995
- [c11]G. Van Brakel, Uwe Gläser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus:
Gate delay fault test generation for non-scan circuits. ED&TC 1995: 308-313 - [c10]Uwe Gläser, Heinrich Theodor Vierhaus:
FOGBUSTER: an efficient algorithm for sequential test generation. EURO-DAC 1995: 230-235 - [c9]Fulvio Corno
Improving topological ATPG with symbolic techniques. VTS 1995: 338-343 - 1994
- [c8]Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus:
Local microcode generation in system design. Code Generation for Embedded Processors 1994: 171-187 - [c7]Uwe Gläser, Heinrich Theodor Vierhaus, M. Kley, A. Wiederhold:
Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. ICCAD 1994: 36-39 - [c6]R. Wolber, Uwe Gläser, Heinrich Theodor Vierhaus:
Testability Analysis for Test Generation in Synchronous Sequential Circuits. ICCD 1994: 350-353 - 1993
- [j6]Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser, Raul Camposano:
Fault behavior and testability of asynchronous CMOS circuits. Microprocess. Microprogramming 38(1-5): 223-228 (1993) - [c5]Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser:
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects. ITC 1993: 83-91 - 1992
- [j5]Uwe Hübner, Wolfgang Meyer, Heinrich Theodor Vierhaus:
CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents. Microprocess. Microprogramming 35(1-5): 377-382 (1992) - [c4]Uwe Gläser, Heinrich Theodor Vierhaus:
MILEF: an efficient approach to mixed level automatic test pattern generation. EURO-DAC 1992: 318-321 - [c3]Uwe Hübner, Heinrich Theodor Vierhaus:
Efficient partitioning and analysis of digital CMOS-circuits. ICCAD 1992: 280-283 - [c2]Ursula Westerholz, Heinrich Theodor Vierhaus:
Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs. ICCD 1992: 472-475 - [c1]Uwe Gläser, Uwe Hübner, Heinrich Theodor Vierhaus:
Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects. ITC 1992: 21-29 - 1991
- [j4]Uwe Hübner, H. Hinsen, M. Hofebauer, Heinrich Theodor Vierhaus:
Mixed level test generation for high fault coverage. Microprocessing and Microprogramming 32(1-5): 791-796 (1991) - 1990
- [j3]Olaf Stern, Heinrich Theodor Vierhaus:
CMOS layout generation for improved testability. Microprocessing and Microprogramming 30(1-5): 509-512 (1990)
1980 – 1989
- 1989
- [j2]Heinrich Theodor Vierhaus:
Testability of non-trivial CMOS faults under realistic conditions. Microprocessing and Microprogramming 27(1-5): 681-686 (1989) - 1988
- [j1]C. Matthäus, B. Krüger-Sprengel, C. Glowacz, Uwe Hübner, Heinrich Theodor Vierhaus:
CMOS fault modeling, test generation and design for testability. Microprocess. Microprogramming 24(1-5): 233-238 (1988)
Coauthor Index
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