A new efficient approach to statistical delay modeling of CMOS digital combinational circuits

This paper presents one of the first attempts to statistically characterize signal delays of basic CMOS digital combinatorial circuits using the transistor level approach. Hybrid analytical/iterative delay expressions in terms of the transistor geometries and technological process variations are created for basic building blocks. Local delays of blocks along specific signal paths are combined together for the analysis of complex combinational VLSI circuits. The speed of analysis is increased by 2 to 4 orders of magnitude relative to SPICE, with about 5–10% accuracy. The proposed approach shows good accuracy in modeling the influence of the “noise” parameters on circuit delay relative to direct SPICE-based Monte Carlo analysis. Examples of statistical delay characterization are shown. The important impact of the proposed approach is that statistical evaluation and optimization of delays in much larger VLSI circuits will become possible.