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Generating instruction sets and microarchitectures from applications

Authors:

Alvin M. DespainAuthors Info & Claims

ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Pages 391 - 396

Published: 06 November 1994 Publication History

Abstract

The design of application-specific instruction set processor(ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design, and instruction set mapping for the application. We present a method that unifies these three design problems with a single formulation: a modified scheduling/allocation problem with an integrated instruction formation process. Micro-operations (MOPs) representing the application are scheduled into time steps. Instructions are formed and hardware resources are allocated during the scheduling process. The assembly code for the given application is obtained automatically at the end of the scheduling process. This approach considers MOP parallelism, instruction field encoding, delay load/store/branch, conditional execution of MOPs and the retargetability to various architecture templates. Experiments are presented to show the power and limitation of our approach. Performance improvement over our previous work is significant.

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Bruce Holmer, Automatic Design of Computer Instruction Sets, Ph.D. thesis, Computer Science Department, Univ. of California, Berkeley, 1993

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Ing-Jer Huang, Co-Synthesis of Instruction Sets and Microarchitectures, Ph.D. thesis, Dept. of Electrical Engineering - Systems, Univ. of Southern California, August 1994

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Cited By

Galuzzi CBertels K(2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1968502.1968509
Rutzig MBeck ACarro L(2009)Dynamically Adapted Low Power ASIPsProceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications10.1007/978-3-642-00641-8_13(110-122)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1007/978-3-642-00641-8_13
Galuzzi CBertels KVassiliadis S(2007)A linear complexity algorithm for the generation of multiple input single output instructions of variable sizeProceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation10.5555/1776200.1776239(283-293)Online publication date: 16-Jul-2007
https://dl.acm.org/doi/10.5555/1776200.1776239
Show More Cited By

Index Terms

Generating instruction sets and microarchitectures from applications
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

November 1994

771 pages

ISBN:0897916905

Chairmen:
Jochen A. G. Jess
Eindhoven Univ. of Technology, Eindhoven, The Netherlands
,
Richard Rudell
Synopsys, Inc., Mountain View, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS: Computer Society

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 06 November 1994

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ICCAD '94

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SIGDA
IEEE-CS

ICCAD '94: International Conference on Computer Aided Design

November 6 - 10, 1994

California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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October 27 - 31, 2024

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Citations

Cited By

Galuzzi CBertels K(2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1968502.1968509
Rutzig MBeck ACarro L(2009)Dynamically Adapted Low Power ASIPsProceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications10.1007/978-3-642-00641-8_13(110-122)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1007/978-3-642-00641-8_13
Galuzzi CBertels KVassiliadis S(2007)A linear complexity algorithm for the generation of multiple input single output instructions of variable sizeProceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation10.5555/1776200.1776239(283-293)Online publication date: 16-Jul-2007
https://dl.acm.org/doi/10.5555/1776200.1776239
Boulytchev D(2006)BURS-based instruction set selectionProceedings of the 6th international Andrei Ershov memorial conference on Perspectives of systems informatics10.5555/1760700.1760740(431-437)Online publication date: 27-Jun-2006
https://dl.acm.org/doi/10.5555/1760700.1760740
Sun FRavi SRaghunathan AJha N(2006)A scalable synthesis methodology for application-specific processorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88641014:11(1175-1188)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TVLSI.2006.886410
Biswas PDutt N(2005)Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set ExtensionsIEEE Transactions on Computers10.1109/TC.2005.15754:10(1216-1226)Online publication date: 1-Oct-2005
https://dl.acm.org/doi/10.1109/TC.2005.157
Sun FRavi SRaghunathan AJha NPileggi LKuehlmann A(2002)Synthesis of custom processors based on extensible platformsProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774667(641-648)Online publication date: 10-Nov-2002
https://dl.acm.org/doi/10.1145/774572.774667
Küçükçakar KJerraya ALavagno LVahid F(1999)An ASIP design methodology for embedded systemsProceedings of the seventh international workshop on Hardware/software codesign10.1145/301177.301190(17-21)Online publication date: 1-Mar-1999
https://dl.acm.org/doi/10.1145/301177.301190
Kalavade ASubrahmanyam POtten RYasuura H(1997)Hardware/software partitioning for multi-function systemsProceedings of the 1997 IEEE/ACM international conference on Computer-aided design10.5555/266388.266543(516-521)Online publication date: 13-Nov-1997
https://dl.acm.org/doi/10.5555/266388.266543
Marwedel PYoffa EDe Micheli GRabaey J(1997)Code generation for core processorsProceedings of the 34th annual Design Automation Conference10.1145/266021.266073(232-237)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266073

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