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CICC 2014: San Jose, California, USA
- Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014. IEEE 2014
- Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology. 1-4 - Jaeha Kim, Si-Jung Yang, Ji-Eun Jang:
PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog. 1-4 - Shih-Hsiung Chien, Li-Te Wu, Ssu-Ying Chen, Ren-Dau Jan, Min-Yung Shih, Ching-Tzung Lin, Tai-Haur Kuo:
An open-loop class-D audio amplifier with increased low-distortion output power and PVT-insensitive EMI reduction. 1-4 - Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu:
A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system. 1-4 - John A. McNeill, Mohammad Ranjbar:
Analog techniques. 1 - Sung-Wan Hong, Gyu-Hyeong Cho:
Inverting buck-boost DC-DC converter for mobile AMOLED display with real-time self-tuned minimum power-loss tracking scheme. 1-4 - Aatmesh Shrivastava, David D. Wentzloff, Benton H. Calhoun:
A 10mV-input boost converter with inductor peak current control and zero detection for thermoelectric energy harvesting. 1-4 - Ismail Cevik, Suat U. Ay:
A 0.8V 140nW low-noise energy harvesting CMOS APS imager with fully digital readout. 1-4 - Yang Shang, Hao Yu, Chang Yang, Yuan Liang, Wei Meng Lim:
A 239-281GHz Sub-THz imager with 100MHz resolution by CMOS direct-conversion receiver with on-chip circular-polarized SIW antenna. 1-4 - Doug C. H. Yu:
New System-in-Package (SiP) Integration technologies. 1-6 - Ed Lee, Mourad El-Gamal:
Bio-systems at Gigahertz. 1 - Keunsoo Song, Sangkwon Lee, Dongkyun Kim, Youngbo Shim, Sangil Park, Bokrim Ko, Duckhwa Hong, Yongsuk Joo, Wooyoung Lee, Yongdeok Cho, Wooyeol Shin, Jaewoong Yun, Hyengouk Lee, Jeonghun Lee, Eunryeong Lee, Jaemo Yang, Haekang Jung, Namkyu Jang, Joohwan Cho, Hyeongon Kim:
A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques. 1-4 - Yingzhe Hu, Tiffany Moy, Liechao Huang, Warren Rieutort-Louis, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma:
3D multi-gesture sensing system for large areas based on pixel self-capacitance readout using TFT scanning and frequency-conversion circuits. 1-4 - Subho Chatterjee, Pramod Kolar, Wei Jian Chan, Jae Y. Ko, Gunjan H. Pandya:
A methodology for yield-specific leakage estimation in memory. 1-4 - Yang Shang, Hao Yu, Peng Li, Xiaojun Bi, Minkyu Je:
A 127-140GHz injection-locked signal source with 3.5mW peak output power by zero-phase coupled oscillator network in 65nm CMOS. 1-4 - Shouhei Kousai, Kohei Onizuka, Song Hu, Hua Wang
, Ali Hajimiri
A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations. 1-8 - Kannan A. Sankaragomathi, Luis Perez, Ramin Mirjalili, Babak A. Parviz, Brian P. Otis:
A 27μW subcutaneous wireless biosensing platform with optical power and data transfer. 1-4 - Martin Kinyua, Ruopeng Wang, Eric G. Soenen:
A 105dBA SNR, 0.0031% THD+N filterless class-D amplifier with discrete time feedback control in 55nm CMOS. 1-4 - Geoffrey Yeap:
Technology-design-manufacturing co-optimization for advanced mobile SoCs. 1-8 - Doug Garrity, Brandt Braswell:
High-performance analog/mixed-signal characterization techniques. 1-53 - Chuang Lu, Marion K. Matters-Kammerer, Reza Mahmoudi, Peter G. M. Baltus:
A millimeter-wave tunable transformer-based dual-antenna duplexer with 50 dB isolation. 1-4 - Mohammad Elbadry, Sachin Kalia, Ramesh Harjani:
A 52% tuning range QVCO with a reduced noise coupling scheme and a minimum FOMT of 196dBc/Hz. 1-4 - Yunjae Suh, Seungnam Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A voltage-scalable 10-b pipelined ADC with current-mode amplifier. 1-4 - Adrian Tang, Mau-Chung Frank Chang
CMOS (Sub)-mm-Wave System-on-Chip for exploration of deep space and outer planetary systems. 1-4 - Zhengyu Wang, Tay Hui Zheng, Dongtian Lu, Sasi Kumar Arunachalam, Xicheng Jiang:
Configurable incremental sigma-delta ADC for DC measure and audio conversion. 1-4 - Kangyeop Choo, Sung-Jin Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hojin Park:
A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology. 1-4 - Hyungwoo Lee, Hyunwoo Cho, Hoi-Jun Yoo:
A 33μW/node Duty Cycle Controlled HBC Transceiver system for medical BAN with 64 sensor nodes. 1-8 - Eric Naviasky, Ken Suyama:
Amplifiers and filters. 1 - Elnaz Ansari, David D. Wentzloff:
A 5mW 250MS/s 12-bit synthesized digital to analog converter. 1-4 - Bram Nauta
Reconfigurable SDR front-end techniques. 1-103 - Chenjie Gu, Larry Nagel:
Advanced simulation techniques. 1 - Rakesh Kumar Palani, Ramesh Harjani:
High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS. 1-4 - Takamaro Kikkawa, Rajiv V. Joshi:
Design technology co-optimization for 10 nm and beyond. 1 - Akshay Visweswaran, John R. Long, Robert Bogdan Staszewski
A 1.2V 110-MHz-UGB differential class-AB amplifier in 65nm CMOS. 1-4 - Qianying Tang, Bongjin Kim, Yingjie Lao, Keshab K. Parhi
True Random Number Generator circuits based on single- and multi-phase beat frequency detection. 1-4 - Chris M. Thomas, Lawrence E. Larson:
A 65 nm CMOS tunable 0.1-to-1.6 GHz distributed transmission line N-path filter with +10 dBm blocker tolerance. 1-4 - Inhee Lee, Yejoong Kim
Circuit techniques for miniaturized biomedical sensors. 1-7 - Feng Zhao, Fa Foster Dai:
A capacitive-coupling technique with phase noise and phase error reduction for multi-phase clock generation. 1-4 - Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang:
Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. 1-4 - Ali Keshavarzi, Dinesh Maheshwari, Derwin Mattos, Ravi Kapre, Sandeep Krishnegowda, Morgan Whately, Sudhir Gopalswamy:
Directions in future of SRAM with QDR-WideIO for high performance networking applications and beyond. 1-6 - Asad A. Abidi, Hao Xu:
Understanding the regenerative comparator circuit. 1-8 - S. Balasubramanian, Vivek Joshi, Torsten Klick, Randy W. Mann, Joseph Versaggi, Akhilesh Gautam, C. Weintraub, G. Kurz, G. Krause, Andreas Kerber, Biju Parameshwaran, Tanya Nigam:
HTOL SRAM Vmin shift considerations in scaled HKMG technologies. 1-4 - Lingamneni Avinash, Christian C. Enz, Krishna V. Palem, Christian Piguet:
Highly energy-efficient and quality-tunable inexact FFT accelerators. 1-4 - Arindam Sanyal, Kareem Ragab, Long Chen, T. R. Viswanathan, Shouli Yan, Nan Sun:
A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. 1-4 - Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
Impact of random telegraph noise on CMOS logic circuit reliability. 1-8 - Kanokwan Limnuson, Hui Lu, Hillel J. Chiel, Pedram Mohseni:
A bidirectional neural interface SoC with an integrated spike recorder, microstimulator, and low-power processor for real-time stimulus artifact rejection. 1-4 - Gregory A. Fish, Daniel K. Sparacin:
Enabling flexible datacenter interconnect networks with WDM silicon photonics. 1-6 - Sudhir S. Kudva, Saurabh Chaubey, Ramesh Harjani:
High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS. 1-4 - Navneet Sharma, Jing Zhang, Qian Zhong, Wooyeol Choi
85-to-127 GHz CMOS transmitter for rotational spectroscopy. 1-4 - Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava
Design Technology co-optimization for N10. 1-8 - Taiyun Chi, Jun Luo, Song Hu, Hua Wang
A multi-phase sub-harmonic injection locking technique for bandwidth extension in silicon-based THz signal generation. 1-4 - Hesham Omran
A robust parasitic-insensitive successive approximation capacitance-to-digital converter. 1-4 - Nicholas Saiz, Nemat Dolatsha, Amin Arbabian:
A 135GHz SiGe transmitter with a dielectric rod antenna-in-package for high EIRP/channel arrays. 1-4 - Wooyoung Jung, Yousof Mortazavi, Brian L. Evans, Arjang Hassibi:
An all-digital PWM-based ΔΣ ADC with an inherently matched multi-bit quantizer. 1-4 - Kun-Da Chu, Ying-Tsang Lu, Chao-Wei Wang, Chih-Ming Hung
A fully integrated translational tracking filter with >40dB blocker attenuation and >68dB harmonic rejection in 40nm for Digital TV tuner applications. 1-4 - Ye-Sheng Kuo, Pat Pannuto
MBus: A 17.5 pJ/bit/chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power. 1-4 - Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult:
Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. 1-8 - Changbyung Park, Tae-Hwang Kong, Gyu-Hyeong Cho:
Low drain voltage S/H type PWM LED current driver for BLU in mobile LCD. 1-4 - Suren Jayasuriya, Dong Yang, Alyosha C. Molnar:
A baseband technique for automated LO leakage suppression achieving > -80dBm in wideband passive mixer-first receivers. 1-4 - Bin Huang, Degang Chen:
A high gain operational amplifier via an efficient conductance cancellation technique. 1-4 - Loai G. Salem
A 45-ratio recursively sliced series-parallel switched-capacitor DC-DC converter achieving 86% efficiency. 1-4 - Edward K. F. Lee, Eusebiu Matei, Van Gang, Jess Shi, Ali Zadeh:
A multiple-output fixed current stimulation ASIC for peripherally-implantable neurostimulation system. 1-4 - Gabriel Alfonso Rincón-Mora:
Miniaturized energy-harvesting piezoelectric chargers. 1-18 - William Lloyd Bircher, Sam Naffziger:
AMD SOC power management: Improving performance/watt using run-time feedback. 1-4 - Ning Lu, Pooja M. Kotecha, Richard A. Wachnik:
Modeling of resistance in FinFET local interconnect. 1-4 - K. R. Raghunandan
Linear current-controlled oscillator for analog to digital conversion. 1-4 - Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang:
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. 1-4 - Renzhi Liu, Larry T. Pileggi, Jeffrey A. Weldon:
A wideband RF receiver with >80 dB harmonic rejection ratio. 1-4 - Behzad Razavi:
Recent developments in RF receivers. 1-78 - John A. McNeill
Lookup-table-based background linearization for VCO-based ADCs. 1-4 - Xiaofei Wang, Weichao Xu, Chris H. Kim:
SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data. 1-4 - Abishek Manian, Behzad Razavi:
A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply. 1-4 - Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez:
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. 1-4 - Mark S. Lundstrom:
NEEDS: Moving nanoscience to nanotechnology. 1-4 - Ming-Shuan Chen, Chih-Kong Ken Yang:
A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS. 1-4 - Min-Gyu Kim, Dongtian Lu, Todd Brooks, Young Ju Kim, Vinay Chandrasekhar, Dale Stubbs, Steven Maughan, Bartomeu Servera Mas, David Yu:
A stereo 110 dB multi-rate audio ΔΣ DAC with Class-G headphone driver. 1-4 - Wei Li, Tao Wang, Jorge A. Grilo, Gabor C. Temes:
A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration. 1-4 - Alex Park, Venkat Narayanan, Keith A. Bowman
Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. 1-4 - Bichen Wu, Jaijeet Roychowdhury:
Efficient per-element distortion contribution analysis via Harmonic Balance adjoints. 1-4 - Seokhyeon Jeong, Inhee Lee, David T. Blaauw, Dennis Sylvester:
A 5.8nW, 45ppm/°C on-chip CMOS wake-up timer using a constant charge subtraction scheme. 1-4 - Cristiano Santos, Pascal Vivet
Thermal modeling methodology for efficient system-level thermal analysis. 1-4 - Saman Saeedi, Azita Emami
An 8GHz first-order frequency synthesizer based on phase interpolation and quadrature frequency detection in 65nm CMOS. 1-4 - Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha:
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. 1-4 - Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu:
A VCO-based current-to-digital converter for sensor applications. 1-4 - Kyeongryeol Bong, Gyeonghoon Kim, Hoi-Jun Yoo:
Energy-efficient Mixed-mode support vector machine processor with analog Gaussian kernel. 1-4 - Yun Yin, Baoyong Chi, Xiaobao Yu, Wen Jia, Zhihua Wang:
An efficiency-enhanced 2.4GHz stacked CMOS power amplifier with mode switching scheme for WLAN applications. 1-4 - Keith Findlater, Adria Bofill, Xavier Revés, Jose Abad:
A HomePlugAV SoC in 40nm CMOS technology. 1-8 - Mazhareddin Taghivand, Yashar Rajavi, Kamal Aggarwal, Ada S. Y. Poon:
An energy harvesting 2×2 60GHz transceiver with scalable data rate of 38-to-2450Mb/s for near range communication. 1-4 - Percy Neyra, Mohammad A. Al-Shyoukh:
A fully-integrated, 90% peak efficiency, 0.99 power factor, AC-DC LED Driver with on-chip direct-AC-connect series startup pre-regulator. 1-4 - Monodeep Kar, Denny Lie, Marilyn Wolf, Vivek De, Saibal Mukhopadhyay:
Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study. 1-4 - Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew J. Turnquist, Mikko Kaltiokallio:
A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS. 1-4 - Seunghyun Lim, Changho Seok, Hyunho Kim, Haryong Song, Hyoungho Ko
A fully integrated electroencephalogram (EEG) analog front-end IC with capacitive input impedance boosting loop. 1-4 - Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, James W. Tschanz, Krishnan Ravichandran, Vivek De:
Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS. 1-4 - Bongjin Kim, Somnath Kundu, Seokkyun Ko, Chris H. Kim:
A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals. 1-4 - Trevor C. Caldwell, David Alldred, Richard Schreier, Hajime Shibata, Yunzhi Dong:
Advances in high-speed continuous-time delta-sigma modulators. 1-8 - Colin McAndrew, Hidetoshi Onodera:
Modeling of advanced devices. 1 - Ramnath Venkatraman, Richard Guo:
Challenges for analog nanoscale technology. 1 - Socrates D. Vamvakos, Charles Boecker, Eric Groen, Alvin Wang, Shaishav Desai, Scott Irwin, Vithal Rao, Aldo Bottelli, Jawji Chen, Xiaole Chen, Prashant Choudhary, Kuo-Chiang Hsieh, Paul Jennings, Haidang Lin, Dan Pechiu, Chethan Rao, Jason Yeung:
A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop. 1-4 - Patrick Rakers, Mohammed Alam, David Newman, Kurt Hausmann, Daniel Schwartz, Mahib Rahman, Mark Kirschenmann:
Multi-mode cellular transceivers for LTE and LTE-Advanced. 1-8 - Shireen Warnock, Robert A. Groves, Hongmei Li, Richard A. Wachnik, Pooja M. Kotecha, Sungjae Lee, Ning Lu, Paul Solomon, Keith Jenkins:
Virtual de-embedding study for the accurate extraction of Fin FET gate resistance. 1-4 - Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban:
POWER8 design methodology innovations for improving productivity and reducing power. 1-9 - Hao San
An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components. 1-4 - Foster F. Dai, Byunghoo Jung:
Low power transceivers and oscillators. 1 - William Walker, Dennis Michael Fischette:
Wireline clocking and equalization. 1 - Gage Hills, Max M. Shulaker, Hai Wei, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra
Robust design and experimental demonstrations of carbon nanotube digital circuits. 1-4 - Jun-Han Choi, Sang-Hui Park, Gyu-Hyeong Cho:
A tri-stack buck converter with gate coupling control (GCC) and quasi adaptive dead time control (QADTC). 1-4 - William McIntyre, Olivier Trescases:
Power management. 1 - Chun-Wei Hsu, Peter R. Kinget
A supply-scalable differential amplifier with pulse-controlled common-mode feedback. 1-4 - Mahdi Elghazali, Manoj Sachdev, Ajoy Opal:
A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology. 1-4 - Run Chen, Hossein Hashemi:
Reconfigurable blocker-resilient receiver with concurrent dual-band carrier aggregation. 1-4 - Kunal Datta, Hossein Hashemi:
A mm-wave class-E 1-bit power modulator. 1-4 - Osama Elhadidy, Sherif Shakib, Keith Krenek, Samuel Palermo, Kamran Entesari:
A 0.18-μm CMOS fully integrated 0.7-6 GHz PLL-based complex dielectric spectroscopy system. 1-4 - Yue Hu, Yang Xu, Un-Ku Moon:
Inherently linear time symmetric pulse width modulation. 1-4 - Yuanming Zhu
A -115dB PSRR CMOS bandgap reference with a novel voltage self-regulating technique. 1-4 - Fengwei An
A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability. 1-4 - Manoj Sachdev, Tetsuya Iizuka:
Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. 1 - Vaibhav Karkare, Hariprasad Chandrakumar, Dejan Rozgic, Dejan Markovic:
Robust, reconfigurable, and power-efficient biosignal recording systems. 1-8 - Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. 1-4 - Jorge A. Grilo, Xicheng Jiang:
Sub-session: Data converter techniques. 1 - Jaebin Choi, Eyal Aklimi, Jared Roseman, David Tsai, Harish Krishnaswamy, Kenneth L. Shepard:
Matching the power density and potentials of biological systems: A 3.1-nW, 130-mV, 0.023-mm3 pulsed 33-GHz radio transmitter in 32-nm SOI CMOS. 1-4 - Azita Emami, Kimo Tam:
Wireline transceivers. 1 - Zheng Zhang
Stochastic testing simulator for integrated circuits and MEMS: Hierarchical and sparse techniques. 1-8 - Hsin-Chieh Chen, Wei-Chung Chen, Ying-Wei Chou, Meng-Wei Chien, Chin-Long Wey, Ke-Horng Chen
Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology. 1-4 - Robert Pawlowski, Joseph Crop, Minki Cho, James W. Tschanz, Vivek De, Thomas Fairbanks, Heather Quinn, Shekhar Borkar, Patrick Yin Chiang:
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS. 1-4 - Tsunenobu Kimoto:
Progress and future challenges of silicon carbide devices for integrated circuits. 1-8 - Won Ho Choi, Saroj Satapathy, John Keane, Chris H. Kim:
A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage. 1-4 - Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE. 1-4 - Jeremy Walker, John G. Kenney, Jesse Bankman, Terry Chen, Steve Harston, Kenneth Lawas, Andrew Lewine, Richard Soenneker, Michael St. Germain, Ward S. Titus, Andrew Y. Wang, Kimo Tam:
A 12.5-Gb/s self-calibrating linear phase detector-based CDR using 0.18μm SiGe BiCMOS. 1-4 - Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang:
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. 1-4 - Ji-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Jong-Ho Kang, Seung-Tak Ryu:
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. 1-4 - Jayant Charthad, Marcus J. Weber, Ting Chia Chang, Mahmoud Saadat, Amin Arbabian:
A mm-sized implantable device with ultrasonic energy transfer and RF data uplink for high-power applications. 1-4 - Behzad Razavi:
The role of translational circuits in RF receiver design. 1-8 - Jack Kenney, Terry Chen, Larry DeVito, Declan Dalton, Stuart McCracken, Richard Soenneker, Ward S. Titus, Todd S. Weigandt:
A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery. 1-4 - Mohammad Al-Shyoukh, Alex Kalnitsky:
A 500nA quiescent current, trim-free, ±1.75% absolute accuracy, CMOS-only voltage reference based on anti-doped N-channel MOSFETs. 1-4 - Mohamed Elkholy, Mohyee Mikhemar, Hooman Darabi, Kamran Entesari:
A 1.6-2.2GHz 23dBm low loss integrated CMOS duplexer. 1-4 - Chia-Hung Chen, Yi Zhang, Tao He, Patrick Yin Chiang, Gabor C. Temes:
A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces. 1-4 - Mohammad Hassan Ghaed, Skylar Skrzyniarz, David T. Blaauw, Dennis Sylvester:
A 1.6nJ/bit, 19.9μA peak current fully integrated 2.5mm2 inductive transceiver for volume-constrained microsystems. 1-4 - Robert A. Groves, Phillip J. Restle, Alan J. Drake, David Shan, Michael G. R. Thomson:
Optimization and modeling of resonant clocking inductors for the POWER8TM microprocessor. 1-4 - Jorge Zarate-Roldan, Salvador Carreon-Bautista, Alfredo Costilla-Reyes
An ultra-low power power management unit with -40dB switching-noise-suppression for a 3×3 thermoelectric generator array with 57% maximum end-to-end efficiency. 1-4 - Joung-Wook Moon, Sung-Geun Kim, Dae Hyun Kwon, Woo-Young Choi:
A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. 1-4 - Pedram Mohseni, Patrick Chiang:
Energy-efficient bio-sensing systems. 1 - Gregory F. Taylor:
The challenges of analog circuits on nanoscale technologies. 1-6 - Vaibhav Tripathi, Boris Murmann
A 160 MS/s, 11.1 mW, single-channel pipelined SAR ADC with 68.3 dB SNDR. 1-4 - Ali Ebrazeh, Pedram Mohseni:
A 14pJ/pulse-TX, 0.18nJ/b-RX, 100Mbps, channelized, IR-UWB transceiver for centimeter-to-meter range biotelemetry. 1-4 - Wanghua Wu, Robert Bogdan Staszewski
Design for test of a mm-Wave ADPLL-based transmitter. 1-8 - Lawrence T. Clark, David Kidd, Vineet Agrawal, Samuel Leshner, Gokul Krishnan:
Independent N and P process monitors for body bias based process corner correction. 1-4 - Mohammed Shoaib, Jie Liu, Matthai Philipose:
Energy scaling in multi-tiered sensing systems through compressive sensing. 1-8 - Vineet Kumar Singh
A 16-band channelizer employing harmonic rejection mixers with enhanced image rejection. 1-4 - Toshiaki Kirihata, Dinesh Somasekhar:
Advanced memory topics. 1 - Jaeha Kim:
Advanced modeling and simulation of state-of-the-art high-speed I/O interfaces. 1-122 - Ramesh Harjani, Saurabh Chaubey:
A unified framework for capacitive series-parallel DC-DC converter design. 1-8 - Kejun Xia, Harihara Indana, Usha Gogineni:
Compact modeling of LDMOS working in the third quadrant. 1-4 - Rick Paul, Aurangzeb Khan:
Design for data-center, low-power and SoCs. 1 - Tanya Nigam, Andreas Kerber:
Reliability modeling of HK MG technologies. 1-8 - Mike Li, Gordon W. Roberts:
Testability and reliability enhancement techniques. 1 - Sandipan Kundu, Julia Hsin-Lin Lu, Erkan Alpman, Hasnain Lakdawala, Jeyanandh Paramesh, Byunghoo Jung, Sarit Zur, Eshel Gordon:
A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN. 1-4 - Bo Wu, Yun Chiu:
An 85-225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS. 1-4 - Peng-Chang Huang, Wen-Chuen Liu, Yi-Chen Liu, Yeong-Chau Kuo, Tai-Haur Kuo:
An analog optimum torque control IC for a 200W wind energy conversion system with over 99% MPPT accuracy, 1.7% THDi and 0.99 power factor. 1-4 - Adam Neale, Manoj Sachdev:
A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC. 1-4 - David Fick, Gyouho Kim, Allan Wang, David T. Blaauw, Dennis Sylvester:
Mixed-signal stochastic computation demonstrated in an image sensor with integrated 2D edge detection and noise filtering. 1-4
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