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Xicheng Jiang
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2010 – 2019
- 2016
- [j13]Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Kun Tan, Aravind Padyana, Vincent Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Bryan Juo-Jung Hung, Massimo Brandolini, Maco Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young J. Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hanson Hung-Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Ray Gomez:
A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver. IEEE J. Solid State Circuits 51(4): 845-859 (2016) - [j12]Boyu Hu
, Fengbo Ren
An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 934-938 (2016) - [c17]Kostas Doris, Alyosha C. Molnar, Xicheng Jiang, Seung-Tak Ryu:
F2: Data-converter calibration and dynamic-matching techniques. ISSCC 2016: 495-497 - [c16]Xicheng Jiang, Axel Thomsen, Piero Malcovati, M.-C. Frank Chang:
EE1: Class of 2025 - Where will be the best jobs? ISSCC 2016: 518 - 2015
- [j11]Lin He, Jiaqi Yang, Duona Luo, Lele Jin, Shuangshuang Zhang, Fujiang Lin, Libin Yao, Xicheng Jiang:
A Speed-Enhancing Dual-Trial Instantaneous Switching Architecture for SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 26-30 (2015) - [j10]Lin He, Guanglong Zhu, Fang Long, Yuncheng Zhang
A Multibit Delta-Sigma Modulator With Double Noise-Shaped Segmentation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 241-245 (2015) - [j9]Zisong Wang
Analysis of Current Efficiency for CMOS Class-B LC Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1345-1352 (2015) - [j8]Lin He, Lele Jin, Jiaqi Yang, Fujiang Lin, Libin Yao, Xicheng Jiang:
Self-Dithering Technique for High-Resolution SAR ADC Design. IEEE Trans. Circuits Syst. II Express Briefs 62-II(12): 1124-1128 (2015) - [c15]Xicheng Jiang, Ed van Tuijl:
Session 5 overview: Analog techniques: Analog subcommittee. ISSCC 2015: 86-87 - [c14]Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Tan, Aravind Padyana, Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Juo-Jung Hung, Massimo Brandolini, Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hung Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Gomez:
A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver. VLSIC 2015: 214- - 2014
- [j7]Khaled Abdelfattah, Sherif Galal, Iuri Mehr, Alex Jianzhong Chen, Chengyue Yu, Maurice Tjie, Ahmet Tekin
A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications. IEEE J. Solid State Circuits 49(8): 1702-1714 (2014) - [j6]Xicheng Jiang, Jungwoo Song, Darwin Cheung, Minsheng Wang, Sasi Kumar Arunachalam:
Integrated Class-D Audio Amplifier With 95% Efficiency and 105 dB SNR. IEEE J. Solid State Circuits 49(11): 2387-2396 (2014) - [j5]Lin He, Yuncheng Zhang
Digital Noise-Coupling Technique for Delta-Sigma Modulators With Segmented Quantization. IEEE Trans. Circuits Syst. II Express Briefs 61-II(6): 403-407 (2014) - [c13]Jorge A. Grilo, Xicheng Jiang:
Sub-session: Data converter techniques. CICC 2014: 1 - [c12]Zhengyu Wang, Tay Hui Zheng, Dongtian Lu, Sasi Kumar Arunachalam, Xicheng Jiang:
Configurable incremental sigma-delta ADC for DC measure and audio conversion. CICC 2014: 1-4 - [c11]Xicheng Jiang, Xinyu Yu, Fang Lin, Felix Cheung, Mike Inerfield, Kevin Li, Abhishek Kamath, Harsh Mehta, Jingbo Duan, Jing Yang, Gautham Krishnamurthy, Sumant Ranganathan, Darwin Cheung, Naga Radha Krishna Damaraju, Jianlong Chen, Dongtian Lu, Vinod Jayakumar, Leon Wang, Dario Soltesz, Hongwei Kong, Min Zhang, David Chang:
A 28 nm analog and audio mixed-signal front end for 4G/LTE Cellular System-on-Chip. ESSCIRC 2014: 471-474 - [c10]Xicheng Jiang, Narayan Prasad Ramachandran, Dae Woon Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang:
Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip. ESSCIRC 2014: 475-478 - [c9]Xicheng Jiang, Piero Malcovati, Vladimir Stojanovic, Tetsuya Lizuka:
F1: Digitally assisted analog and analog-assisted digital in high-performance scaled CMOS process. ISSCC 2014: 510-511 - 2013
- [j4]Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam:
Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers. IEEE J. Solid State Circuits 48(4): 1099-1108 (2013) - [c8]Khaled Abdelfattah, Sherif Galal, Iuri Mehr, Alex Jianzhong Chen, Ahmet Tekin
A direct-battery hookup, fully integrated stereo headphone module with 82 mW output power and 110 dB PSRR. CICC 2013: 1-4 - [c7]Don Thelen, Xicheng Jiang:
Analog techniques I. CICC 2013: 1 - 2012
- [j3]Xicheng Jiang, Jungwoo Song, Jianlong Chen, Vinay Chandrasekhar, Sherif Galal, Felix Y. L. Cheung, Darwin Cheung, Todd Brooks:
A Low-Power, High-Fidelity Stereo Audio Codec in 0.13 µm CMOS. IEEE J. Solid State Circuits 47(5): 1221-1231 (2012) - [c6]Don Thelen, Xicheng Jiang:
Analog Techniques. CICC 2012: 1 - [c5]Xicheng Jiang, Min-Gyu Kim, Felix Cheung, Fang Lin, Hui Zheng, Jianlong Chen, Alex Jianzhong Chen, Darwin Cheung, Khaled Abdelfattah, Seong-Ho Lee, Hanson Hung-Sen Huang, Kishore Kasichainula, Yonghua Cong, Jiangfeng Wu, Chang-Hyeon Lee, George Chih, Yun Tu, Todd Brooks, Edison Jiang, Hongwei Kong, Chaoyang Zhao, Mustafa Keskin:
A 40 nm CMOS analog front end with enhanced audio for HSPA/EDGE multimedia applications. ESSCIRC 2012: 414-417 - [c4]Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam, Todd L. Brooks:
Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices. VLSIC 2012: 18-19 - 2010
- [j2]Minsheng Wang, Xicheng Jiang, Jungwoo Song, Todd Brooks:
A 120 dB Dynamic Range 400 mW Class-D Speaker Driver With Fourth-Order PWM Modulator. IEEE J. Solid State Circuits 45(8): 1427-1435 (2010) - [c3]Sherif Galal, Jurgen van Engelen, Jared Welz, Henrik Jensen, Khaled Abdelfattah, Felix Cheung, Sasi Kumar Arunachalam, Xicheng Jiang, Todd Brooks:
A 32-channel front-end for wireless HID using inverse-STF pre-filtering technique. CICC 2010: 1-4 - [c2]Xicheng Jiang, Jungwoo Song, Todd Brooks, Jianlong Chen, Vinay Chandrasekhar, Felix Cheung, Sherif Galal, Darwin Cheung, Gil-Cho Ahn, Madhulatha Bonu:
A 10mW stereo audio CODEC in 0.13µm CMOS. ISSCC 2010: 82-83
2000 – 2009
- 2009
- [c1]Minsheng Wang, Xicheng Jiang, Jungwoo Song, Todd Brooks:
A 120dB dynamic range 400mW class-D speaker driver with 4th-order PWM modulator. CICC 2009: 13-16 - 2005
- [j1]Xicheng Jiang, Mau-Chung Frank Chang
A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging. IEEE J. Solid State Circuits 40(2): 532-535 (2005)
Coauthor Index
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