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T. R. Viswanathan 0001
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- affiliation: University of Texas at Austin, Department of Electrical and Computer Engineering, USA
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2020 – today
- 2023
- [j14]Sudhanva Vasishta
, K. R. Raghunandan
A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 993-1005 (2023) - 2021
- [c14]Sudhanva Vasishta, K. R. Raghunandan
A Novel Low-Power Single-step Subranging Open-loop Sigma-Delta ADC. MWSCAS 2021: 116-120 - 2020
- [c13]Sudhanva Vasishta, K. R. Raghunandan
Level-Crossing Detection based Low-Power Sigma-Delta ADC for Sensor Applications. MWSCAS 2020: 663-666
2010 – 2019
- 2014
- [c12]K. R. Raghunandan
Linear current-controlled oscillator for analog to digital conversion. CICC 2014: 1-4 - [c11]Arindam Sanyal, Kareem Ragab, Long Chen, T. R. Viswanathan, Shouli Yan, Nan Sun:
A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. CICC 2014: 1-4 - [c10]K. R. Raghunandan
Analog signal processing in deep submicron CMOS technologies using inverters. MWSCAS 2014: 394-397 - [c9]Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan:
A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC. MWSCAS 2014: 1053-1056 - 2013
- [j13]Aslam A. Rafi, T. R. Viswanathan:
Harmonic Rejection Mixing Techniques Using Clock-Gating. IEEE J. Solid State Circuits 48(8): 1862-1874 (2013) - [c8]Adriana Becker-Gomez, Antonio F. Mondragón-Torres, Venkatesh Acharya, Bhaskar Banerjee, Thayamkulangara R. Viswanathan:
A digital bandgap reference. MWSCAS 2013: 213-216 - [c7]Rohit Yadav, K. R. Raghunandan
Operational current to frequency converter. MWSCAS 2013: 900-903 - 2012
- [c6]Joseph Hamilton, Shouli Yan, T. R. Viswanathan:
An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC. CICC 2012: 1-4 - [c5]Aslam A. Rafi, T. R. Viswanathan:
Clock-gated harmonic rejection mixers. CICC 2012: 1-8 - 2011
- [j12]Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan:
A Two-Stage ADC Architecture With VCO-Based Second Stage. IEEE Trans. Circuits Syst. II Express Briefs 58-II(11): 734-738 (2011) - [j11]Ajay Taparia, Bhaskar Banerjee, Thayamkulangara R. Viswanathan:
Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 1960-1968 (2011) - [j10]Ajay Taparia, Bhaskar Banerjee, Thayamkulangara R. Viswanathan:
CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2141-2148 (2011) - 2010
- [j9]Joseph Hamilton, Shouli Yan, T. R. Viswanathan:
A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator. IEEE Trans. Circuits Syst. II Express Briefs 57-II(11): 848-852 (2010)
2000 – 2009
- 2009
- [j8]Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan:
Self-Biased Unity-Gain Buffers With Low Gain Error. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 36-40 (2009) - 2008
- [j7]Adriana Becker-Gomez, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan:
A Low-Supply-Voltage CMOS Sub-Bandgap Reference. IEEE Trans. Circuits Syst. II Express Briefs 55-II(7): 609-613 (2008) - [c4]Ajay Taparia, Thayamkulangara R. Viswanathan:
Low-power short-channel single-ended current-steered CMOS logic-gate for mixed-signal systems. ISCAS 2008: 2290-2293 - [c3]Su Cui, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan, Bhaskar Banerjee:
A highly linear CMOS current-controlled oscillator using a novel frequency detector. ISCAS 2008: 2841-2844 - 2007
- [j6]Raymond T. Perry, Stephen H. Lewis, A. Paul Brokaw, T. R. Viswanathan:
A 1.4 V Supply CMOS Fractional Bandgap Reference. IEEE J. Solid State Circuits 42(10): 2180-2186 (2007) - [j5]Venkatesh Acharya, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan:
CMOS Latch Using Quad for High-Speed Comparators. IEEE Trans. Circuits Syst. II Express Briefs 54-II(5): 407-411 (2007) - 2006
- [c2]Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan:
A Unity-Gain Buffer with Reduced Offset and Gain Error. CICC 2006: 825-828 - 2002
- [j4]Arne E. Buck, Charles L. McDonald, Stephen H. Lewis, T. R. Viswanathan:
A CMOS bandgap reference without resistors. IEEE J. Solid State Circuits 37(1): 81-83 (2002) - 2000
- [j3]Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan:
A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. IEEE J. Solid State Circuits 35(12): 1760-1768 (2000)
1990 – 1999
- 1999
- [j2]K. Nagaraj, F. Chen, T. R. Viswanathan:
Efficient 6-bit A/D converter using a 1-bit folding front end. IEEE J. Solid State Circuits 34(8): 1056-1062 (1999) - 1993
- [c1]N. Sayiner, Henrik V. Sorensen, T. R. Viswanathan:
A Non-uniform Sampling Technique for A/D Conversion. ISCAS 1993: 1220-1223
1980 – 1989
- 1989
- [j1]Vladimir Friedman, Douglas M. Brinthaupt, De-Ping Chen, Timothy W. Deppa, John P. Elward Jr., Evelyn M. Fields, Jeffrey W. Scott, T. R. Viswanathan:
A dual-channel voice-band PCM codec using Sigma Delta modulation technique. IEEE J. Solid State Circuits 24(2): 274-280 (1989)
Coauthor Index
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