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Hao San
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2020 – today
- 2023
- [j17]Eiki Kayama, Kenta Mori, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta:
Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(5): 823-831 (2023) - 2022
- [c29]Tomoharu Yamauchi, Hao San, Nobuyuki Yoshikawa, Olivia Chen
:
A Study on the Efficient Design of Adders Using Adiabatic Quantum-Flux-Parametron Circuits. GCCE 2022: 114-116 - 2021
- [c28]Yuanchi Chen, Hao San:
Linearity Compensation for Conversion Error in Non-binary and Binary Hybrid ADC. ISPACS 2021: 1-2 - [c27]Eiki Kayama, Kenta Mori, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta:
A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology. ISPACS 2021: 1-2 - [c26]Taichi Maebou, Yuanchi Chen, Eiki Kayama, Kenta Mori, Hao San, Tatsuji Matsuura, Masao Hotta:
A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS. ISPACS 2021: 1-2 - [c25]Kenta Mori, Eiki Kayama, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta:
A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier. ISPACS 2021: 1-2 - 2020
- [j16]Hao San
Foreword. IEICE Trans. Electron. 103-C(10): 445 (2020)
2010 – 2019
- 2019
- [j15]Chunhui Pan, Hao San
Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase. IEICE Electron. Express 16(12): 20190280 (2019) - [j14]Chunhui Pan, Hao San
A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(3): 507-517 (2019) - [c24]Haruo Kobayashi, Nene Kushita, Minh Tri Tran
Analog / Mixed-Signal / RF Circuits for Complex Signal Processing. ASICON 2019: 1-4 - [c23]Shuichiro Yamada, Toshiki Ohtsu, Minami Sasaki, Hao San
A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology. ISPACS 2019: 1-2 - 2018
- [j13]Chunhui Pan, Hao San
A 2nd-Order ΔΣAD Modulator Using Dynamic Analog Components with Simplified Operation Phase. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 425-433 (2018) - [j12]Chunhui Pan, Hao San
A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer. IEICE Trans. Electron. 101-C(7): 480-487 (2018) - [c22]Chunhui Pan, Hao San
A 720µW 77.93dB SNDR ΔΣ AD Modulator Using Dynamic Analog Components With Simplified Operation Phase. ISPACS 2018: 442-446 - [c21]Chunhui Pan, Hao San
A 6th-Order Complex Bandpass ΔΣ AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer. ISPACS 2018: 447-452 - 2017
- [j11]Hao San
A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(2): 534-540 (2017) - [c20]Yuki Watanabe, Hayato Narita, Hiroyuki Tsuchiya, Tatsuji Matsuura, Hao San
A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components. ASP-DAC 2017: 15-16 - [c19]Hiroyuki Tsuchiya, Asato Uchiyama, Yuta Misima, Yuki Watanabe, Tatsuji Matsuura, Hao San
Non-binary cyclic ADC with correlated level shifting technique. ASP-DAC 2017: 17-18 - [c18]Koken Chin, Yuta Mishima, Yuki Watanabe, Hiroyuki Tsuchiya, Hao San
A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique. ISPACS 2017: 602-605 - [c17]Hiroyuki Tsuchiya, Yuki Watanabe, Koken Chin, Hao San
The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC. ISPACS 2017: 606-610 - [c16]Yuki Watanabe, Koken Chin, Hiroyuki Tsuchiya, Hao San
Experimental results of reconfigurable non-binary cyclic ADC. ISPACS 2017: 611-615 - [c15]Chunhui Pan, Hao San
A 2nd-order ΔΣAD modulator using ring amplifier and SAR quantizer with simplified operation mode. MIXDES 2017: 45-49 - [c14]Kota Inoue, Tatsuji Matsuura, Akira Hyogo, Hao San
Non-binary cyclic and binary SAR hybrid ADC. MIXDES 2017: 105-109 - 2016
- [c13]Koken Chin, Hao San
Leakage current compensation technique of ESD protection circuit for CMOS operational amplifier. ISPACS 2016: 1-4 - [c12]Chunhui Pan, Hao San
A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer. ISPACS 2016: 1-5 - 2015
- [c11]Yuta Mishima, Toshiki Yamada, Asato Uchiyama, Tatsuji Matsuura, Hao San
A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion. ISPACS 2015: 294-298 - [c10]Chunhui Pan, Hao San
A low-distortion delta-sigma modulator with ring amplifier and passive adder embedded SAR quantizer. ISPACS 2015: 299-302 - 2014
- [j10]Rompei Sugawara, Hao San
Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm. IEICE Trans. Electron. 97-C(4): 308-315 (2014) - [c9]Hao San
An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components. CICC 2014: 1-4 - 2013
- [j9]Hao San
Non-binary Pipeline Analog-to-Digital Converter Based on β-Expansion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 415-421 (2013) - [j8]Rie Suzuki, Tsubasa Maruyama, Hao San
Robust Cyclic ADC Architecture Based on β-Expansion. IEICE Trans. Electron. 96-C(4): 553-559 (2013) - [c8]Takaki Makino, Yukiko Iwata, Yutaka Jitsumatsu, Masao Hotta, Hao San
Rigorous analysis of quantization error of an A/D converter based on β-map. ISCAS 2013: 369-372 - 2010
- [j7]Hao San
Noise-Coupled Image Rejection Architecture of Complex Bandpass DeltaSigmaAD Modulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 390-394 (2010) - [j6]Tomohiko Ogawa, Haruo Kobayashi, Yosuke Takahashi, Nobukazu Takai, Masao Hotta, Hao San
SAR ADC Algorithm with Redundancy and Digital Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 415-423 (2010) - [c7]Tomohiko Ogawa, Tatsuji Matsuura, Haruo Kobayashi, Nobukazu Takai, Masao Hotta, Hao San
Non-binary SAR ADC with digital error correction for low power applications. APCCAS 2010: 196-199
2000 – 2009
- 2009
- [j5]Hao San
Cross-Noise-Coupled Architecture of Complex Bandpass DeltaSigmaAD Modulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 998-1003 (2009) - 2008
- [j4]Hao San
Novel Architecture of Feedforward Second-Order Multibit Delta-Sigma-AD Modulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 965-970 (2008) - [c6]Tomohiko Ogawa, Haruo Kobayashi, Masao Hotta, Yosuke Takahashi, Hao San
SAR ADC algorithm with redundancy. APCCAS 2008: 268-271 - [c5]Ibuki Mori, Keigo Kimura, Yoshihisa Yamada, Haruo Kobayashi, Yasunori Kobori, Santhos Ario Wibowo, Kazuya Shimizu, Masashi Kono, Hao San
High-resolution DPWM generator for digitally controlled DC-DC converters. APCCAS 2008: 914-917 - [c4]Hajime Konagaya, HaiJun Lin, Hao San
ΔΣAD modulator for low power application. APCCAS 2008: 1232-1235 - 2007
- [j3]Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada:
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. IEICE Trans. Electron. 90-C(6): 1181-1188 (2007) - [c3]Hao San
A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS. ASP-DAC 2007: 96-97 - 2006
- [j2]Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada:
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 908-915 (2006) - 2005
- [j1]Jun Otsuki, Hao San
Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths. IEICE Trans. Electron. 88-C(6): 1290-1294 (2005) - 2004
- [c2]Hao San, Haruo Kobayashi, Shinya Kawakami, Nobuyuki Kuroiwa:
An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass \Delta\SigmaAD Modulators. VLSI Design 2004: 151-156
1990 – 1999
- 1999
- [c1]Mohd Asmawi Mohamed Zin, Haruo Kobayashi, Kazuya Kobayashi, Jun-ichi Ichimura, Hao San
A high-speed CMOS track/hold circuit. ICECS 1999: 1709-1712
Coauthor Index
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