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Xuqiang Zheng
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2020 – today
- 2024
- [j18]Hua Xu, Xuqiang Zheng, Zedong Wang, Chen Cai, Wenxiang Zhen, Guojun Yuan, Qinfen Hao, Xuan Guo, Zhi Jin:
A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS. IEICE Electron. Express 21(7): 20240104 (2024) - [j17]Bolin Ren
, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu:
A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. Microelectron. J. 152: 106326 (2024) - [j16]Meng Li
A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. Microelectron. J. 152: 106330 (2024) - [j15]Kewei Xin
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 11-15 (2024) - [c26]Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li:
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j14]Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu:
A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. Microelectron. J. 140: 105905 (2023) - 2022
- [j13]Geng Zhang
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. IEEE Access 10: 96556-96567 (2022) - [j12]Mingche Lai, Geng Zhang
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. 130: 105628 (2022) - 2021
- [c25]Jian Luan, Danyu Wu, Xuqiang Zheng, Chen Cai, Linzhen Wu, Lei Zhou, Jin Wu, Xinyu Liu:
A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency. ESSCIRC 2021: 487-490 - [c24]Chen Cai, Xuqiang Zheng, Yong Chen, Danyu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu:
A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. ESSCIRC 2021: 527-530 - 2020
- [j11]Xuqiang Zheng, Chun Zhang
A CRNN System for Sound Event Detection Based on Gastrointestinal Sound Dataset Collected by Wearable Auscultation Devices. IEEE Access 8: 157892-157905 (2020) - [j10]Xuqiang Zheng
Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. IEEE J. Solid State Circuits 55(6): 1651-1664 (2020) - [j9]Xuqiang Zheng
A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. IEEE J. Solid State Circuits 55(7): 1864-1876 (2020) - [j8]Hongxin Wang
A Robust Visual System for Small Target Motion Detection Against Cluttered Moving Backgrounds. IEEE Trans. Neural Networks Learn. Syst. 31(3): 839-853 (2020)
2010 – 2019
- 2019
- [j7]Huasen Liu, DanYu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo
A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS. IEICE Electron. Express 16(3): 20181079 (2019) - [c23]Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu:
A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. ESSCIRC 2019: 195-198 - [i1]Hongxin Wang, Jigen Peng, Xuqiang Zheng, Shigang Yue:
A Robust Visual System for Small Target Motion Detection Against Cluttered Moving Backgrounds. CoRR abs/1904.04363 (2019) - 2018
- [b1]Xuqiang Zheng:
Design of high-speed SerDes transceiver for chip-to-chip communications in CMOS process. University of Lincoln, UK, 2018 - [j6]Fangxu Lv, Xuqiang Zheng, Feng Zhao
A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. Microelectron. J. 82: 36-45 (2018) - 2017
- [j5]Xuqiang Zheng
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. IEEE J. Solid State Circuits 52(11): 2963-2978 (2017) - [c22]Xuqiang Zheng, Fangxu Lv, Feng Zhao
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. CICC 2017: 1-4 - [c21]Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao
A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. CICC 2017: 1-4 - [c20]Shiquan Fan, Liuming Zhao, Peng Wang, Ran Wei, Xuqiang Zheng, Zenghui Wang, Philip X.-L. Feng:
A battery-less, 255 nA quiescent current temperature sensor with voltage regulator fully powered by harvesting ambient vibrational energy. ISCAS 2017: 1-4 - [c19]Fangxu Lv, Xuqiang Zheng, Shuai Yuan, Ziqiang Wang, Yajun He, Chun Zhang, Zhihua Wang, Jianye Wang:
A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology. MWSCAS 2017: 539-542 - 2016
- [j4]Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7): 939-949 (2016) - [j3]Xuqiang Zheng, Zhijun Wang, Fule Li, Feng Zhao
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1381-1392 (2016) - [c18]Xuqiang Zheng, Chun Zhang, Shuai Yuan, Feng Zhao
An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators. A-SSCC 2016: 85-88 - [c17]Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. ESSCIRC 2016: 305-308 - [c16]Naiwen Zhou, Linghan Wu, Ziqiang Wang, Xuqiang Zheng, Weidong Cao
A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology. NEWCAS 2016: 1-4 - 2015
- [j2]Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1441-1450 (2015) - [c15]Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li:
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. ASICON 2015: 1-4 - [c14]Ke Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang:
A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. CICC 2015: 1-4 - [c13]Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Wen Jia, Chun Zhang, Zhihua Wang:
A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS. CICC 2015: 1-4 - [c12]Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang:
A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS. ESSCIRC 2015: 144-147 - [c11]Weidong Cao
A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS. MWSCAS 2015: 1-4 - [c10]Weidong Cao
A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. NEWCAS 2015: 1-4 - 2014
- [j1]Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Ni Xu, Woogeun Rhee
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS. IEEE Trans. Circuits Syst. II Express Briefs 61-II(4): 209-213 (2014) - [c9]Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology. CICC 2014: 1-4 - 2013
- [c8]Linghan Wu, Ziqiang Wang, Ke Huang, Shuai Yuan, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 10Gb/s analog equalizer in 0.18um CMOS. ASICON 2013: 1-4 - [c7]Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Liji Wu, Zhihua Wang:
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology. ASICON 2013: 1-4 - [c6]Kunzhi Yu, Xuqiang Zheng, Ke Huang, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang:
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. VLSI-DAT 2013: 1-4 - 2012
- [c5]Shijie Hu, Chen Jia, Ke Huang, Chun Zhang, Xuqiang Zheng, Zhihua Wang:
A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS. ISCAS 2012: 309-312 - [c4]Ke Huang, Chen Jia, Xuqiang Zheng, Ni Xu, Chun Zhang, Woogeun Rhee
A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology. ISCAS 2012: 313-316 - [c3]Xuqiang Zheng, Fule Li, Xuan Wang, Chun Zhang:
A current-to-voltage integrator using area-efficient correlated double sampling technique. ISCAS 2012: 2167-2170 - [c2]Ke Huang, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang:
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS. MWSCAS 2012: 932-935 - [c1]Kunzhi Yu, Ziqiang Wang, Xuan Ma, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS. MWSCAS 2012: 936-939
Coauthor Index
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