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CICC 2013: San Jose, California, USA
- Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013, San Jose, CA, USA, September 22-25, 2013. IEEE 2013
- Sakshi Arora, David K. Su, Bruce A. Wooley:
A compact 120-MHz 1.8V/1.2V dual-output DC-DC converter with digital control. 1-4 - Zhidong Liu, Hoi Lee:
A 100V gate driver with sub-nanosecond-delay capacitive-coupled level shifting and dynamic timing control for ZVS-based synchronous power converters. 1-4 - James Lin
, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa:
A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers. 1-4 - Leibo Liu
SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process. 1-4 - Ji-Eun Jang, Si-Jung Yang, Jaeha Kim:
Event-driven simulation of Volterra series models in SystemVerilog. 1-4 - Essam S. Atalla, Frank Zhang, Abdellatif Bellaouar, Poras T. Balsara:
Estimation of passive mixer output bandwidth using switched-capacitor techniques. 1-4 - Greg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken:
The past present and future of design-technology co-optimization. 1-8 - Nan Qi, Baoyong Chi, Yang Xu, Zhou Chen, Jun Xie, Yang Xu, Zheng Song, Zhihua Wang:
An asymmetric dual-channel reconfigurable receiver for GNSS in 180nm CMOS. 1-4 - Rune Kaald, Bjørnar Hernes, Christian Holdo, Frode Telstø, Ivar Løkken:
A 500 MS/s 76dB SNDR continuous time delta sigma modulator with 10MHz signal bandwidth in 0.18μm CMOS. 1-4 - Dennis Michael Fischette, Jaeha Kim:
Wireline transmitter and receiver design techniques. 1 - Vineet Agrawal, N. Kepler, David Kidd, Gokul Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, Taiji Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama:
Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. 1-4 - Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker
Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics. 1-4 - Karim Boutros, Rongming Chu
Recent advances in GaN power electronics. 1-4 - Jabeom Koo
A -173 dBc/Hz @ 1 MHz offset Colpitts oscillator using AlN contour-mode MEMS resonator. 1-4 - Jun Li, Hirohito Mukai, Mehmet Parlak
A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOS. 1-4 - Leibo Liu
An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. 1-4 - David Murphy, Mohyee Mikhemar, Ahmad Mirzaei, Hooman Darabi:
Advances in the design of wideband receivers. 1-8 - Tao Zeng, Kevin Townsend, Jingbo Duan, Degang Chen:
A 15-bit binary-weighted current-steering DAC with ordered element matching. 1-4 - Hasnain Lakdawala, Eric Naviasky:
Analog techniques II. 1 - Maarten De Bock, Pieter Rombouts:
A double-sampling cross noise-coupled Sigma Delta modulator with a reduced amount of opamps. 1-4 - Srikar Bhagavatula, Byunghoo Jung:
A power sensor with 80ns response time for power management in microprocessors. 1-4 - Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong:
A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB. 1-4 - Xiaochen Yang, Robert Payne, Jin Liu:
A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs. 1-4 - Edward K. F. Lee:
An active rectifier/regulator combo circuit for powering biomedical implants. 1-4 - Don Thelen, Xicheng Jiang:
Analog techniques I. 1 - Vaibhav Tripathi, Boris Murmann
Mismatch characterization of small metal fringe capacitors. 1-4 - Mike Peng Li, Takahiro J. Yamaguchi:
Electrical and photonic I/O test and debug. 1-2 - Wolfgang Furtner, Stephan Schacher, Markus Littow, Lionel Cimaz, Pekka E. Leinonen:
BIF - Battery interface standard for mobile devices. 1-8 - Puneet Gupta
Design for nanoscale patterning. 1-52 - Wayne H. Woods, Alberto Valdes-Garcia, Hanyi Ding, Jay Rascoe:
CMOS millimeter wave phase shifter based on tunable transmission lines. 1-4 - Muhammad Ahmadi, Won Namgoong:
A 3.3fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocation. 1-4 - Eldar Zianbetov, Dimitri Galayko
Distributed clock generator for synchronous SoC using ADPLL network. 1-4 - Mehran Bakhshiani, Michael A. Suster, Pedram Mohseni:
A broadband biosensor interface IC for miniaturized dielectric spectroscopy from MHz to GHz. 1-4 - Igor Arsovski, Travis Hebig, John Goss, Paul Grzymkowski, Josh Patch:
Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory. 1-4 - Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull:
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation. 1-4 - Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. 1-4 - Salvatore Levantino
Nonlinearity cancellation in digital PLLs (Invited paper). 1-8 - Jian Xu, Zhi Yang:
A 50 μW/Ch artifacts-insensitive neural recorder using frequency-shaping technique. 1-4 - Eric Naviasky, Hasnain Lakdawala:
Oversampled ADC's. 1 - Jiageng Huang, Shiliang Yang, George Jie Yuan:
A 10-MHz bandwidth 70-dB SNDR 640MS/s continuous-time ΣΔ ADC using Gm-C filter with nonlinear feedback DAC calibration. 1-4 - Hsin-Lun Li, Chia-Cheng Pao, Bo-Ming Chen, Chien-Hung Tsai:
AOT-controlled dual-mode AVP buck regulator with AEAF mechanism. 1-4 - Mihai A. T. Sanduleanu
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI. 1-4 - Manideep Gande, Ho-Young Lee, Hariprasath Venkatram, Jon Guerber, Un-Ku Moon:
Blind background calibration of harmonic distortion based on selective sampling. 1-4 - James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada:
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset. 1-4 - Shupeng Sun, Xin Li, Chenjie Gu:
Structure-aware high-dimensional performance modeling for analog and mixed-signal circuits. 1-4 - Trevor C. Caldwell, David Alldred, Zhao Li:
A reconfigurable ΔΣ modulator with up to 100 MHz bandwidth using flash reference shuffling. 1-4 - Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Miki Tanaka, Shinji Tanaka, Koji Nii:
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. 1-4 - Naga Rajesh, Shanthi Pavan:
A lumped component programmable delay element for Ultra-Wideband beamforming. 1-4 - Brian Otis:
Low power chip & system design for biomedicai applications. 1-53 - Jean-Pierre Colinge, Sang H. Dhong:
Prospective for nanowire transistors. 1-8 - Richard A. Wachnik, Sungjae Lee, Li-Hong Pan, Ning Lu, Hongmei Li, Raphael Bingert, Mai Randall, Scott K. Springer, Christopher S. Putnam:
Gate stack resistance and limits to CMOS logic performance. 1-4 - Saurabh Saxena
A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. 1-4 - Boris Murmann
A/D converter circuit and architecture design for high-speed data communication. 1-78 - Mohammad Ranjbar, John A. McNeill
Nyquist rate A/D converters. 1 - Yung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li:
A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching. 1-4 - Bongjin Kim, Weichao Xu, Chris H. Kim:
A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal. 1-4 - Sedigheh Hashemi, Behzad Razavi:
A 7.1-mW 1-GS/s ADC with 48-dB SNDR at Nyquist rate. 1-4 - Gerrit den Besten, Harold G. Hanson, Ranjeet K. Gupta:
Current-steering pre-emphasis transmitter with continuously tuned line terminations for optimum impedance match and maximum signal drive range. 1-4 - Jae-Won Nam
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS. 1-4 - Burak Çatli, Ali Nazemi, Tamer A. Ali, Siavash Fallahi, Yang Liu, Jaehyup Kim, Mohammed M. Abdul-Latif, Mahmoud Reza Ahmadi, Hassan Maarefi, Afshin Momtaz, Namik Kocaman:
A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications. 1-4 - Dandan Zhang, Haigang Yang, Zhujia Chen, Wei Li, Zhihong Huang, Lijiang Gao, Wen-rui Zhu:
A fast-locking digital DLL with a high resolution time-to-digital converter. 1-4 - Salvatore Levantino
Advanced digital phase-locked loops. 1-95 - Siva V. Thyagarajan, Ali M. Niknejad, Christopher D. Hull:
A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOS. 1-4 - Shuai Chen, Hao Li, Liqiong Yang, Zongren Yang, Weiwu Hu, Patrick Yin Chiang:
A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS. 1-4 - Christine P. Tan, Congshu Zhou, Yi Tian, Chang Liu, Hein-Mun Lam, Jian Zhang, Mark Lu:
Design for manufacturing layout analyses correlate layout to physico-chemical yield loss mechanisms. 1-4 - Hariprasath Venkatram, Benjamin P. Hershberg, Taehwan Oh, Manideep Gande, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
Parallel gain enhancement technique for switched-capacitor circuits. 1-4 - Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada:
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. 1-4 - Man Pun Chan, Philip K. T. Mok
A monolithic digitally controlled ripple-based DC-DC converter with digital inductor current sensor. 1-4 - Hegong Wei, Peng Zhang, Bibhudatta Sahoo, Behzad Razavi:
An 8-Bit 4-GS/s 120-mW CMOS ADC. 1-4 - Khurram Muhammad, Ming-Cho Chen, Kai-Hung Wang, Kuang-Ping Ma, Yu-Lin Hiseh, Wei-Show Hsu, Yuan-Yu Fu, Meng-Chang Lee, Shuo-Yuan Hsiao, Chih-Ming Hung
An adaptive predistorter for wireless LAN RFSoC with embedded PA and T/R switch in 55nm CMOS. 1-4 - Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection. 1-8 - Ken Takeuchi:
Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory. 1-6 - Q. Guo, Michael A. Suster, R. Surapaneni, Carlos H. Mastrangelo, Darrin J. Young:
Design and characterization of electronic sensing system for a 13 × 13 biomechanical ground reaction sensor array. 1-4 - Koji Nii, Toshiaki Kirihata:
Advanced memory topics. 1 - Takao Nomura, Ryo Mori, Munehiro Ito, Koji Takayanagi, Toshihiko Ochiai, Kazuki Fukuoka, Kazuo Otsuga, Koji Nii, Sadayuki Morita, Tomoaki Hashimoto, Tsuyoshi Kida, Junichi Yamada, Hideki Tanaka:
Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor. 1-4 - Khaled Abdelfattah, Sherif Galal, Iuri Mehr, Alex Jianzhong Chen, Ahmet Tekin
A direct-battery hookup, fully integrated stereo headphone module with 82 mW output power and 110 dB PSRR. 1-4 - Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou:
A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. 1-4 - Thomas W. Andre, Syed M. Alam, Dietmar Gogl, C. K. Subramanian, Hal Lin, W. Meadows, X. Zhang, Nicholas D. Rizzo, Jason Janesky, D. Houssameddine, Jon M. Slaughter:
ST-MRAM fundamentals, challenges, and applications. 1-8 - Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim:
A 9.2-GHz digital phase-locked loop with peaking-free transfer function. 1-4 - Hans Tuinhout:
Characterization of matching variability and low-frequency noise for mixed-signal technologies. 1-111 - X. Shawn Wang, Xin Wang, Fei Lu, Li Wang, Rui Ma, Zongyu Dong, Li Sun, Albert Z. Wang, C. Patrick Yue
A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design. 1-4 - Shunli Ma, Wei Fei, Hao Yu, Junyan Ren:
A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line. 1-4 - Matthew Loh, Azita Emami-Neyestanak
Capacitive proximity communication with distributed alignment sensing for origami biomedical implants. 1-4 - Ephrem Wu
Interconnect and package design of a heterogeneous stacked-silicon FPGA. 1-8 - Jong Seok Park, Shouhei Kousai, Hua Wang
A fully differential ultra-compact broadband transformer based quadrature generation scheme. 1-4 - Yue Chao, Howard C. Luong
Transformer-based dual-band VCO and ILFD for wide-band mm-Wave LO generation. 1-4 - Maofeng Yang, Nikolas P. Papadopoulos, Czang-Ho Lee, William S. Wong
A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays. 1-4 - Sang-Soo Lee, Edward Boling, Augustine Kuo, Robert Rogenmoser:
A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications. 1-4 - Min-Chie Jeng, Cheng Hsiao, Ke-Wei Su, Chung-Kai Lin:
Circuit reliability simulation using TMI2. 1-7 - Yousr Ismail, Chang-Jin Kim, Chih-Kong Ken Yang:
A bipolar >40-V driver in 45-nm SOI CMOS technology. 1-4 - Chih-Hung Chen, David Chen, Ryan Lee, Peiming Lei, Daniel Wan:
Thermal noise modeling of nano-scale MOSFETs for mixed-signal and RF applications. 1-8 - Xuan Zhang
Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOS. 1-4 - Anatoly Yakovlev, Jihoon Jang, Daniel Pivonka, Ada S. Y. Poon:
A 11μW Sub-pJ/bit reconfigurable transceiver for mm-sized wireless implants. 1-4 - Bharan Giridhar, Matthew Fojtik, David Fick, Dennis Sylvester, David T. Blaauw:
Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating. 1-4 - Andrea Mazzanti, Earl W. McCune Jr.:
RF building blocks. 1 - Alvin Li, Shiyuan Zheng, Jun Yin
A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliers. 1-4 - Yida Duan, Elad Alon:
A 12.8GS/s time-interleaved SAR ADC with 25GHz 3dB ERBW and 4.6b ENOB. 1-4 - Gaurav Bawa, Alex Q. Huang
Switched-capacitor filter based Type-III compensation for switched-mode Buck converters. 1-4 - Sherif H. Abdelhalem, Prasad S. Gudem, Lawrence E. Larson:
Hybrid transformer-based tunable integrated duplexer with antenna impedance tracking loop. 1-4 - Seokhyeon Jeong, Jae-Yoon Sim, David T. Blaauw, Dennis Sylvester:
65nW CMOS temperature sensor for ultra-low power microsystems. 1-4 - Dongkyung Park, Hoi Lee:
A 40V 10W 93%-efficiency current-accuracy-enhanced dimmable LED driver with adaptive timing difference compensation for solid-state lighting applications. 1-4 - Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder
FireBird: PowerPC e200 based SoC for high temperature operation. 1-4 - Behzad Razavi:
Charge steering: A low-power design paradigm. 1-8 - Li Wang, Xin Wang, Zitao Shi, Rui Ma, Chen Zhang, Zongyu Dong, Fei Lu, Hui Zhao, Albert Z. Wang:
Scalable behavior modeling for 3D field-programmable ESD protection structures. 1-4 - Swaroop Ghosh:
Energy centric model of SRAM write operation for improved energy and error rates. 1-4 - Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS. 1-4 - Mezyad Amourah, Sandeep Krishnegowda, Morgan Whately:
A novel OTA-based fast lock PLL. 1-4 - Moongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. 1-4 - Mike Peng Li, Masashi Shimanouchi, Hsinho Wu:
Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013). 1-8 - Christoph Sandner
Power management. 1 - Ashkan Borna, Yanjie Wang, Chris Hull, Hua Wang
A fully integrated highly linear receiver with automatic IP2 calibration schemes for multi-standard applications. 1-4 - Guanhua Wang, Yun Chiu:
Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering. 1-4 - Albert Z. Wang:
Concurrent design of ESD protection and ICs for optimization and prediction. 1-34 - Trent McConaghy, Brian Chen:
Variation and analog modeling. 1 - Richard Schenker, Vivek Singh:
Foundations for scaling beyond 14nm. 1-4 - Aliakbar Homayoun, Behzad Razavi:
A 5-GHz 11.6-mW CMOS receiver for IEEE 802.11a applications. 1-4 - Ron Kapusta
Sampling circuits that break the kT/C thermal noise limit. 1-6 - Colin C. McAndrew, Ik-Sung Lim, Brandt Braswell, Doug Garrity:
Corner models: Inaccurate at best, and it only gets worst ... 1-4 - Vahid Majidzadeh, Alexandre Schmid
A 16-channel, 359 μW, parallel neural recording system using Walsh-Hadamard coding. 1-4 - Yen-Po Chen, Yoonmyung Lee
45pW ESD clamp circuit for ultra-low power applications. 1-4 - Chengrui Le, Mitchell Kline, Daniel Lin Gerber, Seth R. Sanders, Peter R. Kinget
A stackable switched-capacitor DC/DC converter IC for LED drivers with 90% efficiency. 1-4 - John E. Bowers:
Trends, Possibilities and Limitations of Silicon Photonic Integrated Circuits and Devices. 1-89 - Barend van Liempd, Jonathan Borremans, Sungwoo Cha, Ewout Martens, Hans Suys, Jan Craninckx
IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm. 1-4 - Sabrina Liao, Mark Horowitz:
A Verilog piecewise-linear analog behavior model for mixed-signal validation. 1-5 - Tao Tong, Xuan Zhang
A fully integrated battery-connected switched-capacitor 4: 1 voltage regulator with 70% peak efficiency using bottom-plate charge recycling. 1-4 - Kiyohiko Sakakibara, Yaichiro Miura, Toshio Kumamoto, Susumu Tanimoto:
Analysis of deviation from Pelgrom scaling law in Vth variability of pocket-implanted MOSFET. 1-4 - Abhishek Ghosh, Sudhakar Pamarti
A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtered-dithering based linearization. 1-4 - John F. Bulzacchelli:
Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates. 1-8 - Steve J. A. Majerus
Power management circuits for a 15-μA, implantable pressure sensor. 1-4 - Payam M. Farahabadi, Kambiz K. Moez:
Compact high-power 60 GHz power amplifier in 65 nm CMOS. 1-4 - Seung-Hwan Song, Ki Chul Chun, Chris H. Kim:
A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications. 1-4 - Jaeha Kim, Jiho Lee, Do-Gyoon Song, Taehwan Kim, Kyung-Hoon Kim, Seobin Jung, Sangho Youn:
Discretization and discrimination methods for design, verification, and testing of analog/mixed-signal circuits. 1-8 - Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa:
A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. 1-4 - Samuel Palermo, Kimo Tam:
High-speed wireline timing recovery & PLLs. 1 - William Lepkowski, Seth J. Wilk, J. Kam, Trevor J. Thornton
40V MESFETs fabricated on 32nm SOI CMOS. 1-4 - Yao-Chia Liu, Wei-Zen Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Yen-Wei Lee, Min-Shueh Yuan:
A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector. 1-4 - Jong Seok Park, Taiyun Chi, Hua Wang
An ultra-broadband compact mm-wave butler matrix in CMOS for array-based MIMO systems. 1-4 - Shuai Wang, Jun Han, Yang Li, Yifan Bo, Xiaoyang Zeng:
A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms. 1-4 - Jie Xu, Jianyun Hu, Berkehan Ciftcioglu, Hui Wu:
A 4-15-GHz ring oscillator based injection-locked frequency multiplier with built-in harmonic generation. 1-4 - Kai Li, Mitsuyoshi Ito, Atsushi Esumi:
A 1/10000 lower error rate achievable SSD controller with Message-Passing Error Correcting Code architecture and Parity Area Combined scheme. 1-3 - Chenjie Gu:
Algorithmic nonlinear macromodeling: Challenges, solutions and applications in Analog/Mixed-Signal validation. 1-8 - Jingjing Chen, Weiyang Liu, Peng Feng, Haiyong Wang, Nanjian Wu:
A 2.4 GHz energy-efficient 18-Mbps FSK transmitter in 0.18 μm CMOS. 1-4 - Kyoungtae Lee
A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLA. 1-4 - Ali Sheikholeslami, Hirotaka Tamura:
Design metrics for blind ADC-based wireline receivers. 1-8 - Nagendra Krishnapura
A model-agnostic technique for simulating per-element distortion contributions. 1-4 - Christophe Antoine, Stephen O'Driscoll:
Microsystems for biomedical and sensing applications. 1 - Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar:
A split-foundry asynchronous FPGA. 1-4 - Hidetoshi Onodera, Yu Kevin Cao:
AMS verification in advanced technologies. 1 - Koji Kotani:
Highly efficient CMOS rectifier assisted by symmetric and voltage-boost PV-cell structures for synergistic ambient energy harvesting. 1-4 - Khondker Z. Ahmed, Saibal Mukhopadhyay:
A 110nA synchronous boost regulator with autonomous bias gating for energy harvesting. 1-4 - Visvesh S. Sathe, Arif Rahman:
Energy efficient SoC design. 1 - Vinay K. Chippa, Hrishikesh Jayakumar
Energy-efficient recognition and mining processor using scalable effort design. 1-4 - Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Won Lee, Seong-Ook Jung:
All-digital 90° phase-shift DLL with a dithering jitter suppression scheme. 1-4 - Ghavam G. Shahidi:
From 2D-planar to 3D-non-planar device architecture: A scalable path forward? 1-8 - Lei Wan, Yajie Qin, Patrick Chiang, Guoping Chen, Ran Liu, Zhiliang Hong:
High-sensitivity photodetection sensor front-end, detecting organophosphourous compounds for food safety. 1-4 - Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada:
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. 1-4 - Sriramkumar Venugopalan, Vivek Joshi, Luis Zamudio, Matthias Goldbach, Gert Burbach, Ralf Van Bentum, Sriram Balasubramanian:
SRAM read current variability and its dependence on transistor statistics. 1-4 - Larry Nagel, Colin C. McAndrew:
AMS system simulation techniques. 1 - Sadok Aouini, Jean-Francois Bousquet
A programmable analog frequency-locked loop for VCO characterization and test with 8 ppm resolution. 1-4 - Alexey Lopich, Piotr Dudek:
A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array. 1-4 - Fei Chen, Yu Li, Deyuan Lin, Huiying Zhuo, Woogeun Rhee
A 1.14mW 750kb/s FM-UWB transmitter with 8-FSK subcarrier modulation. 1-4 - Sudip Shekhar, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper:
Design considerations for low-power receiver front-end in high-speed data links. 1-8 - Vojkan Vidojkovic, Viki Szortyka, Khaled Khalaf, Giovanni Mangraviti
CMOS low-power transceivers for 60GHz multi Gbit/s communications. 1-8 - Zhimiao Chen, Yifan Wang, Joern Driesen, Fabio Garzia, Stefan Koehler, Frank Henkel, Ralf Wunderlich, Stefan Heinen:
Comparison of modeling approaches through hierarchical behavioral modeling of a GNSS receiver front-end. 1-4 - Philip K. T. Mok
Single-inductor-multiple-output DC-DC converter design. 1-70 - Geert Hellings, Shih-Hung Chen, Dimitri Linten, Mirko Scholz, Guido Groeseneken
Quasi-3D method: Time-efficient TCAD and mixed-mode simulations on finFET technologies. 1-4 - Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. 1-4 - Wonsik Yu, KwangSeok Kim, SeongHwan Cho:
A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator. 1-4 - Andrew R. Macpherson, James W. Haslett, Leonid Belostotski
A 5GS/s 4-bit time-based single-channel CMOS ADC for radio astronomy. 1-4 - Seunghyun Oh, Nathan E. Roberts, David D. Wentzloff:
A 116nW multi-band wake-up receiver with 31-bit correlator and interference rejection. 1-4
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