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Masaya Miyahara
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2020 – today
- 2023
- [j41]Masaya Miyahara, Zule Xu, Takehito Ishii, Noritoshi Kimura:
A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications. IEICE Trans. Electron. 106(10): 521-528 (2023) - 2021
- [j40]Junjun Qiu
, Zheng Sun
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. IEEE J. Solid State Circuits 56(12): 3741-3755 (2021)
2010 – 2019
- 2019
- [j39]Zule Xu, Anugerah Firdauzi
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. IEICE Trans. Electron. 102-C(7): 520-529 (2019) - [j38]Jian Pang
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. IEEE J. Solid State Circuits 54(5): 1375-1390 (2019) - [c38]Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC 2019: 267-270 - 2018
- [j37]Akira Matsuzawa, Masaya Miyahara
SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier. IEICE Electron. Express 15(5) (2018) - [j36]Tohru Kaneko, Yuya Kimura, Masaya Miyahara
A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells. IEICE Trans. Electron. 101-C(4): 197-205 (2018) - [j35]Abdel Martinez Alonso
A 7GS/s Complete-DDFS-Solution in 65nm CMOS. IEICE Trans. Electron. 101-C(4): 206-217 (2018) - [j34]Abdel Martinez Alonso
A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS. IEEE J. Solid State Circuits 53(10): 2840-2849 (2018) - [c37]Masaya Miyahara, Yukiya Endo, Kenichi Okada
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. VLSI Circuits 2018: 115-116 - 2017
- [j33]Tohru Kaneko, Yuya Kimura, Masaya Miyahara
A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input. IEICE Trans. Electron. 100-C(6): 539-547 (2017) - [j32]Anugerah Firdauzi
High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. IEICE Trans. Electron. 100-C(6): 548-559 (2017) - [j31]Rui Wu
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits 52(11): 2871-2891 (2017) - [c36]Akira Matsuzawa, Masaya Miyahara:
SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier. ASICON 2017: 24-27 - [c35]Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON 2017: 1025-1028 - [c34]Abdel Martinez Alonso
A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS. A-SSCC 2017: 181-184 - [c33]Masaya Miyahara, Akira Matsuzawa:
An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. CICC 2017: 1-4 - [c32]Abdel Martinez Alonso
A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS. ESSCIRC 2017: 151-154 - [c31]Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. ISSCC 2017: 424-425 - 2016
- [j30]Zhijie Chen, Masaya Miyahara
Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC. IEICE Trans. Electron. 99-C(6): 623-631 (2016) - [j29]Lilan Yu, Masaya Miyahara
Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques. IEICE Trans. Electron. 99-C(6): 641-650 (2016) - [j28]Zhijie Chen, Masaya Miyahara
A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC. IEICE Trans. Electron. 99-C(8): 963-973 (2016) - [j27]Abdel Martinez Alonso
A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture. IEICE Trans. Electron. 99-C(10): 1200-1210 (2016) - [j26]Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2435-2443 (2016) - [j25]Yu Hou, Zhijie Chen, Masaya Miyahara
A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2473-2482 (2016) - [j24]Teerachot Siriburanon
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits 51(6): 1385-1397 (2016) - [j23]Lilan Yu
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers. IEEE J. Solid State Circuits 51(10): 2210-2221 (2016) - [j22]Zule Xu
A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. IEEE J. Solid State Circuits 51(10): 2345-2356 (2016) - [c30]Lilan Yu, Masaya Miyahara, Akira Matsuzawa:
A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers. A-SSCC 2016: 65-68 - [c29]Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada
An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. A-SSCC 2016: 109-112 - [c28]Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain. A-SSCC 2016: 309-312 - [c27]Zule Xu, Anugerah Firdauzi
A 2 GHz 3.1 mW type-I digital ring-based PLL. ESSCIRC 2016: 205-208 - [c26]Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder. ESSCIRC 2016: 249-252 - [c25]Tohru Kaneko, Yuya Kimura, Koji Hirose, Masaya Miyahara, Akira Matsuzawa:
A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter. ESSCIRC 2016: 253-256 - [c24]Anugerah Firdauzi
A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. ISCAS 2016: 57-60 - [c23]Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC 2016: 248-249 - 2015
- [j21]Yu Hou, Takamoto Watanabe, Masaya Miyahara
An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(2): 466-475 (2015) - [j20]Zule Xu, Seungjong Lee, Masaya Miyahara
Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(2): 476-484 (2015) - [j19]Tohru Kaneko, Masaya Miyahara
A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency. IEICE Trans. Electron. 98-C(4): 315-321 (2015) - [j18]James Lin
An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers. IEEE J. Solid State Circuits 50(6): 1399-1411 (2015) - [j17]James Lin
Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1518-1527 (2015) - [c22]Abdel Martinez Alonso
A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture. ASICON 2015: 1-4 - [c21]Zule Xu, Masaya Miyahara, Akira Matsuzawa:
A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. A-SSCC 2015: 1-4 - [c20]Lilan Yu, Masaya Miyahara, Akira Matsuzawa:
A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers. A-SSCC 2015: 1-4 - [c19]Teerachot Siriburanon
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC 2015: 1-3 - [c18]Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada
19.5 An HCI-healing 60GHz CMOS transceiver. ISSCC 2015: 1-3 - [c17]Zhijie Chen, Masaya Miyahara, Akira Matsuzawa:
A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC. VLSIC 2015: 64- - 2014
- [j16]Sanroku Tsukamoto, Masaya Miyahara
A 7-bit 1-GS/s Flash ADC with Background Calibration. IEICE Trans. Electron. 97-C(4): 298-307 (2014) - [j15]Jeonghoon Han, Masaya Miyahara
Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator. IEICE Trans. Electron. 97-C(4): 316-324 (2014) - [j14]James Lin
An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2400-2410 (2014) - [j13]Ahmed Musa, Wei Deng, Teerachot Siriburanon
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits 49(1): 50-60 (2014) - [c16]Wei Deng, Ahmed Musa, Teerachot Siriburanon
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC 2014: 21-22 - [c15]James Lin
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. A-SSCC 2014: 85-88 - [c14]Takamoto Watanabe, Yu Hou, Masaya Miyahara, Akira Matsuzawa:
All-digital 0.016mm2 reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS. ICECS 2014: 21-24 - [c13]Tomohito Terasawa, Yuji Kamiya, Hiroyuki Kawashima, Kenichiro Imai, Masanobu Suzuki, Takamoto Watanabe, Nobuyuki Taguchi, Manabu Sawada, Yu Hou, Yoshiyuki Hirooka, Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa:
Radio receiver front-end using time-based all-digital ADC (TAD). ICECS 2014: 471-473 - [c12]Kenichi Okada
20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. ISSCC 2014: 346-347 - [c11]Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada
22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers. ISSCC 2014: 388-389 - 2013
- [j12]Hyunui Lee, Yusuke Asada, Masaya Miyahara
A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 422-433 (2013) - [j11]Fei Li, Masaya Miyahara
Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs. IEICE Trans. Electron. 96-C(4): 568-576 (2013) - [j10]Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara
A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells. IEICE Trans. Electron. 96-C(6): 813-819 (2013) - [j9]Hyunui Lee, Masaya Miyahara
Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers. IEICE Trans. Electron. 96-C(6): 838-849 (2013) - [j8]Fei Li, Masaya Miyahara
A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs. IEICE Trans. Electron. 96-C(6): 903-911 (2013) - [j7]Hyunui Lee, Masaya Miyahara
A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2508-2515 (2013) - [j6]Kenichi Okada
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. IEEE J. Solid State Circuits 48(1): 46-65 (2013) - [c10]James Lin
A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers. CICC 2013: 1-4 - [c9]Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa:
A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. CICC 2013: 1-4 - [c8]Wei Deng, Ahmed Musa, Teerachot Siriburanon
A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. ISSCC 2013: 248-249 - [c7]Hyunui Lee, Masaya Miyahara, Akira Matsuzawa:
A 12-bit interpolated pipeline ADC using body voltage controlled amplifier. NEWCAS 2013: 1-4 - [c6]Zule Xu, Masaya Miyahara, Akira Matsuzawa:
A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS. NEWCAS 2013: 1-4 - 2012
- [j5]Daehwa Paik, Masaya Miyahara
An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 456-470 (2012) - [j4]Hong Phuc Ninh, Masaya Miyahara
A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching. IEICE Trans. Electron. 95-C(6): 1017-1025 (2012) - [c5]Kenichi Okada
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. ISSCC 2012: 218-220 - 2011
- [c4]Daehwa Paik, Masaya Miyahara, Akira Matsuzawa:
An analysis on a pseudo-differential dynamic comparator with load capacitance calibration. ASICON 2011: 461-464 - [c3]Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa:
A time-domain architecture and design method of high speed A-to-D converters with standard cells. A-SSCC 2011: 353-356 - [c2]James Lin
A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique. ISCAS 2011: 21-24 - 2010
- [j3]Daehwa Paik, Yusuke Asada, Masaya Miyahara
An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 402-414 (2010)
2000 – 2009
- 2009
- [c1]Kaziiya Kojima, Yasuhiro Toriyama, Toru Taniguchi, Masaya Miyahara, Akira Matsuzawa:
Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof. ICECS 2009: 687-690 - 2008
- [j2]Masaya Miyahara
A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 469-475 (2008) - 2007
- [j1]Masaya Miyahara, Akira Matsuzawa:
The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time. IEICE Trans. Electron. 90-C(6): 1165-1171 (2007)
Coauthor Index
[j39] [j37] [j36] [j35] [j34] [c37] [j33] [j32] [j31] [c36] [c35] [c34] [c33] [c32] [c31] [j30] [j29] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [j21] [j20] [j19] [j18] [j17] [c22] [c21] [c20] [c19] [c18] [c17] [j16] [j15] [j14] [j13] [c16] [c15] [c14] [c13] [c12] [c11] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [c10] [c9] [c8] [c7] [c6] [j5] [j4] [c5] [c4] [c3] [c2] [j3] [c1] [j2] [j1]
Ken-ichi Okada
aka: Kenichi Okada
aka: Kenichi Okada
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