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TW201426965A - 半導體晶粒封裝與封裝上封裝裝置 - Google Patents

半導體晶粒封裝與封裝上封裝裝置 Download PDF

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Publication number
TW201426965A
TW201426965A TW102145797A TW102145797A TW201426965A TW 201426965 A TW201426965 A TW 201426965A TW 102145797 A TW102145797 A TW 102145797A TW 102145797 A TW102145797 A TW 102145797A TW 201426965 A TW201426965 A TW 201426965A
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Taiwan
Prior art keywords
package
layer
conductive layer
semiconductor die
redistribution
Prior art date
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TW102145797A
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English (en)
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TWI543332B (zh
Inventor
Jing-Cheng Lin
Jui-Pin Hung
Po-Hao Tsai
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Taiwan Semiconductor Mfg
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Publication of TW201426965A publication Critical patent/TW201426965A/zh
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Publication of TWI543332B publication Critical patent/TWI543332B/zh

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Abstract

在多種實施例中，TPV的形成機制包含多層導電層及/或凹陷形成於晶粒封裝與封裝上封裝(PoP)裝置中，其採用TPV形成接合結構。多層導電層中的一者可作為TPV之主導電層的保護層。保護層較不易氧化，且與焊料接觸時較慢形成金屬間化合物(IMC)。TPV中的凹陷可填有另一晶粒封裝的焊料，使IMC層低於TPV的表面，進而強化接合結構。

Description

半導體晶粒封裝與封裝上封裝裝置
本發明係關於半導體封裝結構，更特別關於其通過封裝通孔(TPV)之結構。
半導體裝置已應用於多種電子設備，比如個人電腦、手機、數位相機、及其他電子設備。半導體裝置的製作方法通常為依序沉積絕緣或介電層、導電層、與半導體層於半導體基板上，並微影圖案化上述層狀物以形成電路構件與元件於其上。
半導體產業持續縮減結構的最小尺寸，以持續改良多種電子構件(比如電晶體、二極體、電阻、電容、或類似構件)的積體密度，使單位面積所能整合的構件更多。在某些應用中，較小的電子構件亦需較小的封裝，其比之前的封裝具有更小面積及/或更低高度。
如此一來，新發展的封裝技術如封裝上封裝(PoP)中，頂部封裝的裝置晶粒接合至底部封裝的另一裝置晶粒。藉由新的封裝技術可增加封裝的積體度，但較新的半導體封裝技術仍需面對製程挑戰。
本發明一實施例提供之半導體晶粒封裝，包括： 半導體晶粒；成型化合物，封裝至少部份的半導體晶粒；通過封裝通孔，形成於成型化合物中，其中通過封裝通孔與半導體晶粒相鄰，其中通過封裝通孔包括第一導電層與第二導電層，且其中第一導電層填入通過封裝通孔的第一部份，且第二導電層填入通過封裝通孔的第二部份；以及重佈線結構，其中重佈線結構包括重佈線層，其中通過封裝通孔與半導體晶粒電性連接至重佈線層，且其中重佈線層使半導體晶粒具有扇出式結構。
本發明一實施例提供之半導體晶粒封裝，包括：半導體晶粒；通過封裝通孔，形成於半導體晶粒封裝中，其中通過封裝通孔與半導體晶粒相鄰，其中通過封裝通孔包括導電層與凹陷；以及重佈線結構，其中重佈線結構包括重佈線層，其中通過封裝通孔與半導體晶粒電性連接至重佈線層，且再佈線層使半導體晶粒具有扇出式結構，且其中凹陷與重佈線層分別位於導電層的相反兩端上。
本發明一實施例提供之封裝上封裝裝置，包括：第一晶粒封裝，包括：第一半導體晶粒，以及通過封裝通孔，其中通過封裝通孔與第一半導體晶粒相鄰，其中通過封裝通孔包括第一導電層與第二導電層；以及第二晶粒封裝，包括：第二半導體晶粒，以及外部連接物，具有焊料，其中第二晶粒封裝的外部連接物接合至第一晶粒封裝的通過封裝通孔。
d3I、d3II‧‧‧深度
D1、D1I、D1II、D2、D2I、D2II、D3I、D3II、D4V‧‧‧厚度
D1A、D2A、HIII、HIV、HV‧‧‧高度
X、Y‧‧‧區域
100‧‧‧封裝結構
105、130‧‧‧基板
110、120、120’‧‧‧封裝
111、123‧‧‧成型化合物
112、113、121‧‧‧半導體晶粒
114、116‧‧‧接合打線
115、117、127、117V‧‧‧連接物
117I、117II‧‧‧接合焊料
118‧‧‧金屬墊
119‧‧‧內連線結構
122、122A、122B、122C、122D、122I、122II、122III、122III’、122IV、122IV’、122V、122V’、122”‧‧‧TPV
122’‧‧‧導電柱
124、213‧‧‧重佈線層
125‧‧‧重佈線結構
126、145‧‧‧外部連接物
141‧‧‧氧化銅層
142、142’、142I、142II、142IV、142V‧‧‧IMC層
201‧‧‧載板
202‧‧‧黏著層
203、203I、203II、203III、203IV、203V‧‧‧第一導電層
204‧‧‧電鍍晶種層
205‧‧‧光阻層
206‧‧‧開口
207、207I、207II、207III、207IV、207V‧‧‧第二導電層
209‧‧‧表面
210‧‧‧膠層
212、214‧‧‧鈍化層
219‧‧‧帶狀物
223I、223II、223IV、223V‧‧‧第三導電層
224III、224IV、224V‧‧‧凹陷
225V‧‧‧第四導電層
260、260’、260I、260II、260III、260IV、260V‧‧‧接合結構
第1A圖係某些實施例中，封裝結構的透視圖； 第1B圖係某些實施例中，一晶粒封裝接合至另一晶粒封裝的剖視圖；第2A至2P圖係某些實施例中，製備封裝上封裝(PoP)裝置的製程剖視圖；以及第3A-3B、4A-4B、5A-5B、6A-6C、7A-7C、8A-8C圖係某些實施例中，晶粒封裝與封裝上封裝(PoP)裝置的剖視圖。
下述內容將詳述本發明實施例如何製作與使用。可以理解的是，這些實施例所提供的多種可行發明概念，以實施於多種特定方式。然而這些特定實施例僅用以說明而非侷限本發明。
自從積體電路發明以來，多種電子構件如電晶體、二極體、電阻、電容、或類似物的積體密度持續改良，使半導體產業持續快速成長。積體密度改良的主要部份為持續縮減結構的最小尺寸，使單位面積所能整合的構件更多。
上述改良通常為二維改良，即積體構件主要位於半導體晶圓的表面上。雖然大幅改良的微影技術已改良二維積體電路，但二維密度仍具有物理限制。物理限制之一為構件的最小尺寸。此外，當單一晶片具有越多裝置時需要越複雜的設計。
三維積體電路(3D IC)可解決上述限制。在某些3D IC的製程中，多個晶圓各自具有積體電路。上述晶圓可切割成晶粒。封裝具有不同裝置的晶粒，再將對準的裝置接合。通過封裝通孔(TPV)或通過成型通孔(TMV)，已廣泛應用於實施3D IC。TPV通常用於3D IC與堆疊晶粒，以提供電性連接及/或幫助散熱。
第1A圖係某些實施例中，封裝結構100的透視圖。封裝結構100具有封裝110接合至另一封裝120，且封裝120更接合至另一基板130。每一封裝110與120包含至少一半導體晶粒(未圖示)，因此又稱作晶粒封裝。半導體晶粒包含半導體基板以用於製作半導體積體電路，而半導體電路可形成於半導體基板之中及/或之上。半導體基板可為包含半導體材料的任何結構，包含但不限於基體矽、半導體晶圓、絕緣層上矽(SOI)基板、或矽鍺基板。其他半導體材料如III族元素、IV族元素、與V族元素亦可用於半導體基板。半導體基板可進一步包含多個隔離結構(未圖示)如淺溝槽隔離(STI)結構或局部氧化矽(LOCOS)結構。隔離結構可定義並隔離多種微電子元件。可形成於半導體基板中的多種微電子元件包含電晶體如金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、雙極接面電晶體(BJT)、高電壓電晶體、高頻電晶體、p型通道場效電晶體(PFET)及/或n型通道場效電晶體(NFET)、電阻、二極體、電容、電感、熔絲、或其他合適元件。用以形成多種微電子元件的多種製程包含沉積、蝕刻、佈植、光微影、回火、及/或其他合適製程。微電子元件內連線後可形成積體電路裝置，比如邏極裝置、記憶裝置如SRAM、RF裝置、輸入/輸出(I/O)裝置、系統單晶片(SoC)裝置、上述之組合、或其他合適的裝置。在某些實施例中，封裝120包含通過封裝通孔(TPV)並作為中介物。
基板130可為雙馬來醯亞胺三嗪(BT)樹脂、FR-4(織造的玻璃纖維與環氧樹脂黏結劑組成的耐火複合材料)、陶瓷、玻璃、塑膠、帶狀物、膜狀物、或其他可負載導電墊或導電平台的支撐材料以接觸導電端。在某些實施例中，基板130為多層電路板。封裝110經由連接物115接合至封裝120，而封裝120藉由外部連接物145接合至基板130。在某些實施例中，外部連接物145為接合的凸塊結構如接合的焊料凸塊，或具有接合焊料層的接合銅柱。上述焊料可包含或不包含鉛。
第1B圖係某些實施例中，封裝110位於封裝120上的剖視圖。如第1B圖所示，封裝110包含兩個半導體晶粒112與113，且半導體晶粒113位於半導體晶粒112上。然而封裝110可包含單一半導體晶粒，或超過兩個半導體晶粒。在某些實施例中，半導體晶粒112與113之間具有膠層(未圖示)。半導體晶粒112與113可具有多種半導體元件，如前述用於半導體晶粒的元件。半導體晶粒112係接合至基板105。基板105可具有多種材料及/或化合物，如前述之基板130。在某些實施例中，半導體晶粒112經由接合打線114電性連接至基板105中的導電元件(未圖示)。同樣地，半導體晶粒113經由接合打線116電性連接至基板105中的導電單元。封裝110亦包含成型化合物111，其覆蓋半導體晶粒112與113及接合打線114與116。封裝110亦包含多個連接物117用於外部連接。連接物117係形成於金屬墊118上，而金屬墊118藉由內連線結構119電性連接至接合打線114與116。上述內連線結構119包含通孔與金屬線路。
如第1B圖所示的某些實施例中，封裝120包含半導 體晶粒121與圍繞半導體晶粒121的TPV 122。封裝120亦包含重佈線結構125，其包含一或多個重佈線層(RDL)124。重佈線層124為金屬內連線層，具有金屬線路與通孔並被介電材料包圍。重佈線層124可用以實施半導體晶粒121的扇出式設計。如第1B圖所示，外部連接物126如球格陣列(BGA)可貼合至重佈線結構125上的金屬墊(未圖示)。如第1B圖所示，TPV 122係連接至封裝110的連接物117。半導體晶粒121與外部連接物126分別位於重佈線結構125的相反兩端上。半導體晶粒121經由連接物127連接至重佈線結構125。
在某些實施例中，封裝110的連接物117其組成可為焊料。在某些實施例中，連接物117可為銅柱，其末端具有焊料。連接物117的焊料接合至TPV 122露出的銅表面，且TPV 122填有銅。然而露出的銅表面可能因大氣形成氧化銅。如此一來，在TPV 122的表面上，比如第1B圖所示之TBV 122D之表面可能形成氧化銅層141。雖然可施加迴焊劑於TPV 122的表面上以移除形成在TPV 122表面上的氧化銅層，但某些實施例不適用移除製程。如此一來，所有或至少部份的氧化銅層141將保留於某些TPV 122如TPV 122D上。由於連接物126的焊料與氧化銅層141無法接合良好，兩者的接點脆弱並影響良率與可信度。
即使迴焊劑可移除TPV如TPV 122A、122B、與122C的氧化銅層，連接物126與TPV的銅之間的直接接觸會產生金屬間化合物(IMC)如銅錫化合物。如第1B圖所示的某些實施例中，IMC層142係形成於連接物126與TPV 122A、122B、與122C 的銅之間。由於封裝120上的不同元件具有不同的熱膨脹係數(CTE)，封裝120將彎曲於封裝製程之中及/或之後。上述彎曲現象，會使接合結構如封裝110與120之間的連接物126與TPV 122產生應力。上述應力可能會使連接物117與TPV 122形成的接合結構260碎裂，對封裝上封裝(PoP)結構的良率與可信度造成不良的影響。
在露出TPV 122前且未將TPV接合至連接物前，可先形成保護層(未圖示)如焊料膏層、有機可焊膏層(OSP)、或其他可用的保護層成於TPV上。然而在形成TPV 122後形成保護層的作法，可能會將具有封裝晶粒(或基板)的載板傳輸至處理系統或腔室，及/或處理基板以形成保護層。在形成保護層前，需處理TPV 122的表面如迴焊劑處理，以移除形成的氧化銅層141。上述額外製程操作的成本過高。如此一來，需要新的機制形成接合結構於晶粒封裝之間，以避免上述問題。
第2A至2P圖某些實施例中，製備PoP元件的流程剖視圖。如第2A圖所示，黏著層(又稱膠層)202位於載板201上。然而，亦可施加其他材料用於載板201。在某些實施例中，黏著層202係沉積或壓合至載板201上。黏著層202之組成可為膠或壓合材料如箔。在某些實施例中，黏著層202為光敏性材料，並在封裝120的封裝製程完成後，以紫外線或雷射照射載板201即可輕易分離載板201與黏著層202。舉例來說，黏著層202可為3M公司所售之光熱轉換(LTHC)塗層。在某些實施例中，黏著層202為感熱材料。在某些實施例中，黏著層202進一步包含膠層(未圖示)。舉例來說，膠層可為晶粒貼合膜(DAF)、高分 子如聚醯亞胺或聚苯并噁唑(PBO)、或阻焊膜改良黏著性。
如第2B圖所示的某些實施例中，接著形成電鍍晶種層204於黏著層202上。在某些實施例中，電鍍晶種層204之組成為銅，其形成方法為物理氣相沉積(PVD)。然而電鍍晶種層亦可為其他導電膜。舉例來說，電鍍晶種層204之組成可為鈦、鈦合金、銅、及/或銅合金。鈦合金與銅合金可包含其他元素如銀、鉻、鎳、錫、金、鎢、或上述之組合。在某些實施例中，電鍍晶種層204之厚度介於約0.1μm至約1.0μm之間。在某些實施例中，電鍍晶種層204包含擴散阻障層，其形成順序早於沉積電鍍晶種層。電鍍晶種層204可作為其下方層的黏著層。在某些實施例中，擴散阻障層之組成為鈦，其厚度介於約0.01μm至約0.1μm之間。然而擴散阻障層亦可為其他材料，比如氮化鉭或其他可用材料，且其厚度亦不限於上述範圍。在某些實施例中，擴散阻障層之形成方法為PVD。
如第2C圖所示的某些實施例中，沉積電鍍晶種層204後接著形成光阻層205於其上。光阻層205的形成方法可為濕式製程如旋轉塗佈製程，或乾式製程如乾膜。在形成光阻層205後，可圖案化光阻層205以形成開口206。之後可將導電材料填入開口206以形成第1B圖中的TPV。上述圖案化製程包含光微影與顯影光阻。在某些實施例中，開口206的寬度介於約40μm至約260μm之間。在某些實施例中，開口206的深度介於約60μm至約300μm之間。
在某些實施例中，接著將第一導電層203鍍於電鍍晶種層204之表面上。第一導電層203不會與焊料形成IMC，即 使與焊料形成IMC也比銅與焊料形成IMC的速率慢。此外，第一導電層203暴露於環境中(比如空氣)時，也比銅更不易氧化。在某些實施例中，第一導電層203之組成為鎳。然而，其他導電材料亦可符合第一導電層203所需的品質，比如鉑、金、銀、錫、錫合金如錫銀合金、錫銀銅合金、錫銅合金、錫銀銅-鉍、或上述之組合。在某些實施例中，第一導電層203的厚度D1介於約0.1μm至約30μm之間。
如第2D圖所示的某些實施例中，在形成第一導電層203後，將第二導電層207鍍於第一導電層203上並填入開口206。在某些實施例中，第二導電層207之厚度D2介於約50μm至約300μm之間。
在填入溝槽的電鍍製程後，以蝕刻製程如乾式或濕式蝕刻製程移除光阻層205。如第2E圖所示之某些實施例中，載板201上的剖視結構已移除光阻層205，並露出開口206中的導電材料如導電柱122’。
接著如第2F圖所示的某些實施例，半導體晶粒121經膠層210貼合至載板201上的表面209。在某些實施例中，膠層210為晶粒貼合膜(DAF)，其組成可為環氧樹脂、酚樹脂、丙烯酸樹脂、氧化矽填充物、或上述之組合。第2F圖顯示半導體晶粒121的連接物127與表面209分別位於半導體晶粒121的相反兩端上。接著施加液態成型化合物於載板201上的電鍍晶種層204的表面上，以填入導電柱122’與半導體晶粒121之間的空間，並覆蓋半導體晶粒121與導電柱122’。在某些實施例中，半導體晶粒121直接貼合至黏著層202的表面上。先移除半導體 晶粒121下的電鍍晶種層204的話，成型化合物材料將施加至電鍍晶種層202的表面上。接著進行熱製程硬化成型化合物材料，使其轉換為成型化合物123。在成型化合物123形成後將包圍導電柱122’，使其轉換為TPV 122”如第2G圖所示。
在某些實施例中，之後進行平坦化製程以移除多餘的成型化合物123，以露出TPV 122”與半導體晶粒121的連接物127。在某些實施例中，平坦化製程為研磨製程。在某些實施例中，平坦化製程為化學機械研磨(CMP)製程。在某些實施例中，平坦化製程後的結構如第2H圖所示。
如第2I圖所示之某些實施例中，在平坦化製程後形成重佈線結構125於第2H圖之結構的表面上。第2I圖中的重佈線結構125包含以一或多個鈍化層如212與214絕緣的重佈線層213。重佈線層213包含金屬線路與導電通孔。重佈線層213之組成可為導電材料，並直接接觸TPV 122”與半導體晶粒121的連接物127。在某些實施例中，重佈線層213之組成為鋁、鋁合金、銅、或銅合金。然而重佈線層213之組成可為其他種類的導電材料。鈍化層212與214之組成為介電材料，並於外部連接物126接合至基板130時緩解接合應力。在某些實施例中，鈍化層212與214之組成為高分子如聚醯亞胺、聚苯并噁唑(PBO)、或苯并環丁烯(BCB)。鈍化層214經圖案化後形成開口(未圖示)，以露出部份重佈線層213作為接合墊(未圖示)。在某些實施例中，凸塊下金屬化(UBM)層(未圖示)係形成於接合墊上。UBM層亦可襯墊鈍化層214之開口的側壁。在某些實施例中，重佈線層213可為單層結構。
重佈線結構、接合結構、與其形成方法可參考申請人早先申請之美國申請號13/427,753(發明名稱：用於多晶片封裝的凸塊結構，申請日：2012/3/22)與美國申請號13/338,820(發明名稱：封裝的半導體裝置與封裝半導體裝置的方法，申請日：2011/12/28)。上述申請案如附件所示。
如第2J圖所示的某些實施例中，在形成重佈線結構125後，將外部連接物126安置或接合於重佈線結構125的接合墊(未圖示)上。電性測試載板201上的晶粒，以確認晶粒功能及TPV 122”、重佈線結構125、與接合的外部連接物126之品質。在某些實施例中，亦進行可信度測試。
如第K圖所示的某些實施例中，在將外部連接物126安置於接合墊上後，翻轉第2J圖的結構並將其貼合至帶狀物219。在某些實施例中，帶狀物219為光敏材料，可於封裝製程完成後以紫外光(UV)照射載板201，使帶狀物219與載板201易於分離。之後移除載板201與黏著層202。可採用雷射提供熱以移除黏著層。第2L圖顯示移除載板201與黏著層202後的結構。如第2M圖所示的某些實施例中，移除黏著層202後接著移除電鍍晶種層204。移除電鍍晶種層204的方法可為蝕刻如濕蝕刻。為移除銅，可採用磷酸與雙氧水的水溶液。若電鍍晶種層204包含擴散阻障層如鈦，可採用氫氟酸移除電鍍晶種層204。在某些實施例中，移除部份導電層203以形成凹陷(未圖示)於每一TPV 122”中。
如第2N圖所示的某些實施例中，移除電鍍晶種層204後接著移除膠層210。如前所述，膠層210之組成可為晶粒 貼合膜(DAF)，其移除方法可為包含氫氧化四甲基銨(TMAH)與二甲基亞碸(DMSO)的濕式剝除製程。在某些實施例中，可保留(不移除)膠層210以利散除半導體晶粒121產生的熱。
不論是否移除膠層210(端視需要而定)，接著將封裝的晶粒切割成個別的封裝晶粒。上述切割製程可為晶粒切割。在完成切割後，自封裝晶粒移除帶狀物219。如第2O圖所示的某些實施例，封裝(晶粒封裝)120’已移除帶狀物219。舉例來說，第2O圖的區域X包含兩個TPV 122。
接著將封裝110置於封裝120’上。如第2P圖所示的某些實施例中，封裝110之連接物117係接合至封裝120’的TPV 122”。由於第一導電層203的存在，連接物117與TPV 122”形成的接合結構260’具有較薄的IMC層142’。IMC層142’係由連接物117的焊料與導電材料如鎳所形成。鎳錫的IMC層之形成速率，比焊料及銅(如銅錫)的IMC層之形成速率慢。第2P圖的區域Y包含接合結構260’與IMC層142’。
第3A圖係某些實施例中，第2O圖之區域X的放大圖。區域X中的TPV 122”被成型化合物123包圍。TPV 122”連接至重佈線層213，且鈍化層212與214絕緣重佈線層213。每一TPV 122”的第一導電層203具有高度D1A，且第二導電層207具有高度D2A。在某些實施例中，高度D1A介於約0.5μm至約10μm之間。在某些實施例中，高度D2A介於約50μm至約300μm之間。第3B圖係某些實施例中，第2P圖之區域Y的放大圖。在第3B圖中，IMC層142’係形成於焊料的錫與第一導電層203之間。舉例來說，若第一導電層203為鎳，則形成包含鎳錫的IMC層。在 某些實施例中，IMC層142’的厚度介於約0.5μm至約10μm之間。IMC層142’遠比第1B圖中的IMC層142(包含銅錫)薄。如此一來，第一導電層203可作為TPV 122”之第二導電層207的保護層。
此外由於第一導電層203較不易氧化，因此其形成氧化層(如第1B圖之氧化層141)的風險大幅下降，甚至不會形成氧化層。若在接合連接物117前先以迴焊劑進行預處理，可更一致地移除表面氧化層。如此一來，形成於封裝110與120’之間的接合結構260比沒有第一導電層203所形成的接合結構堅固。用以形成第二導電層207的整合鍍系統亦可用以形成第一導電層203，使形成第一導電層203的額外成本更合理且更值得。
以保護導電層(如第一導電層203)作為部份TPV可降低TPV的表面氧化與前述的IMC，其概念可延伸至其他種類的實施例。第4A圖係某些實施例中的TPV 122I。如第4A圖所示，第三導電層223I緊鄰第一導電層203I，而第一導電層203I緊鄰第二導電層207I。上述結構的製程順序係在鍍第一導電層203I前，先將第三導電層223I鍍於電鍍晶種層204上。如第4B圖所示的某些實施例中，TPV 122I接合至連接物117以形成接合結構260I。
第三導電層223I之組成為焊料。TPV 122I中的焊料層(如第三導電層223I)可讓接合結構260I中接合的焊料，延伸至成型化合物123的表面下。如此一來，靠近TPV 122I表面的IMC層142I將由靠近TPV 122I表面處，移動至TPV 122I表面下 以強化接合結構260I。在某些實施例中，第一導電層203I之厚度D1I、第二導電層207I之厚度D2I、以及IMC層142I之厚度，與第3A及3B圖中對應的元件厚度相同。在某些實施例中，第三導電層223I之厚度D31介於約0.5μm至約30μm之間。如第4B圖所示的某些實施例中，接合焊料117I自成型化合物123之表面下陷的深度d3I介於約0.5μm至約30μm之間。深度d3I與厚度D3I大致相同。
第5A圖顯示某些實施例中的TPV 122II。如第5A圖所示，第三導電層223II形成於第一導電層203II上。如前述之第2M圖，移除部份的第一導電層以形成凹陷(未圖示)於每一TPV中。若以第3A圖之結構形成第5A圖之結構，可用移除第一導電層203II如鎳的蝕刻化學品形成凹陷。若以第4A圖之結構形成第5A圖之結構，可用移除焊料的蝕刻化學品形成凹陷。接著將第三導電層223II(如焊料膏)填入凹陷。如第5A圖所示，某些第三導電層223II突出於TPV 122II上。如第5B圖所示的某些實施例中，TPV 122II接合至連接物117以形成接合結構260II。
第三導電層223II之組成為焊料。與第4A及4B圖之結構一樣，具有焊料層如第三導電層223II的TPV 122II，可讓接合結構260II中接合的焊料，延伸至成型化合物123的表面下。如此一來，靠近TPV 122II表面的IMC層142II將由靠近TPV 122II表面處，移動至TPV 122II表面下。在某些實施例中，第一導電層203II之厚度D1II、第二導電層207II之厚度D2II、以及IMC層142II之厚度，與第3A及3B圖中對應的元件厚度相同。在某些實施例中，第三導電層223II之厚度D3II介於約0.5μm至約30μm 之間。在某些實施例中，凹陷部份的高度介於約0.5μm至約30μm之間。在某些實施例中，第5B圖的接合焊料117II自成型化合物123之表面下陷的深度d3II介於約0.5μm至約30μm之間。
第6A圖為某些實施例中的TPV 122III。TPV 122III與第3A圖之TPV 122”類似，但TPV 122III之第二導電層207III之組成為焊料而非銅，且第一導電層203III之組成為銅或鈦。焊料具有良好導電性，且比銅便宜。以銅作為第二導電層可降低製作成本。在移除電鍍晶種層204時，將移除銅或鈦組成的第一導電層203III，如前述之第2M圖。用以蝕刻電鍍晶種層204的化學品可用以移除第一導電層203III。如第6B圖所示之某些實施例中，移除第一導電層203III後形成TPV 122III’以及凹陷224III。在某些實施例中，凹陷224III的高度HIII介於約0.5μm至約30μm之間。
如第6C圖所示的某些實施例中，TPV 122III’接合至連接物117以形成接合結構260III。連接物117的焊料填入靠近TPV 122III’表面的凹陷。
第7A圖為某些實施例中的TPV 122IV，其與第4A圖之TPV 122I類似。第一導電層203IV與第一導電層203I類似。第二導電層207IV與第二導電層207I類似。然而TPV 122IV之第三導電層223IV之組成為銅或鈦而非焊料。如前述之第2M圖，當蝕刻移除電鍍晶種層204時，將同時移除銅或鈦組成的第三導電層223IV。用於蝕刻電鍍晶種層204化學品，亦可用於移除第一導電層203IV。如第7B圖所示的某些實施例中，移除第三導電層223IV後形成TPV 122IV’。在某些實施例中，仍有薄層的第 三導電層223IV保留於第一導電層203IV上。在移除所有或部份的第三導電層223IV後，即形成凹陷224IV。在某些實施例中，凹陷224IV之高度HIV介於約0.5μm至約30μm之間。
如第7C圖所示之某些實施例中，TPV 122IV’接合至連接物117以形成接合結構260IV。接合物117之焊料填入靠近TPV 122IV’其表面的凹陷。若保留於TPV 122IV’中薄層的第三導電層223IV被氧化，形成的氧化物在接合製程後可採用蝕刻移除(比如被迴焊劑蝕刻)或溶解於焊料中。如第7C圖所示的某些實施例中，IMC層142IV係形成於第一導電層203IV與連接物117的焊料之間。IMC層142IV與第3B圖之IMC層142’的厚度相同。
第8A圖係某些實施例的TPV 122V，其與第7A圖之TPV 122IV類似。第三導電層223V與第三導電層223IV相同，第一導電層203V與第一導電層203IV相同，且第二導電層207V與第二導電層207IV相同。然而如第8A圖所示，第四導電層225V係形成於第一導電層203V與第三導電層223V之間。如前所述，第三導電層223V之組成可為銅或鈦。第四導電層225V之組成為焊料。在某些實施例中，第四導電層225V之厚度D4V介於約0.3μm至約2μm之間。
在前述移除電鍍晶種層204之步驟中，亦蝕刻移除由銅或鈦組成的第三導電層223V。如第8B圖所示的某些實施例中，移除第三導電層223V後形成TPV 122V’與凹陷224V。在某些實施例中，凹陷224V之高度HV介於約0.3μm至約2μm之間。
如第8C圖所示的某些實施例中，TPV 122V’接合至連接物117V以形成接合結構260V。連接物117V之焊料填入靠近 TPV122V’其表面的凹陷。如第8C圖所示之某些實施例中，IMC層142V係形成於第一導電層203V與連接物117V的焊料之間。IMC層142V的厚度範圍與第3B圖之IMC層142’的厚度範圍類似。
在形成主要導電層前，先進行一或多道電鍍製程以形成上述TPV中的額外導電層。不同的電鍍製程可進行於整合系統中，以節省額外的製作成本。藉由移除電鍍晶種層時的額外蝕刻，可形成上述TPV末端的凹陷。若凹陷的形成方法為移除組成為銅或鈦的導電層，則蝕刻移除電鍍晶種層的步驟可同時移除導電層以形成凹陷。如此一來，形成凹陷的步驟只會增加蝕刻時間。若被移除的導電層其組成並非銅或鈦，則需採用不同的蝕刻製程以形成凹陷。然而蝕刻形成凹陷的製程與蝕刻移除電鍍晶種層的製程可進行於整合系統中，以節省凹陷的製作成本。然而額外導電層的保護層較不會氧化，也較不會與焊料形成IMC，可改善形成於晶粒封裝之間的接合結構之良率與可靠度。上述凹陷亦可改善形成於晶粒封裝之間的接合結構之良率與可靠度。
在多種實施例中，TPV的形成機制包含多層導電層及/或凹陷形成於晶粒封裝與封裝上封裝(PoP)裝置中，其採用TPV形成接合結構。多層導電層中的一者可作為TPV之主導電層的保護層。保護層較不易氧化，且與焊料接觸時較慢形成IMC。TPV中的凹陷可填有另一晶粒封裝的焊料，使IMC層低於TPV的表面，進而強化接合結構。
在某些實施例中，半導體晶粒封裝包括半導體晶 粒與形成其中的TPV。TPV與半導體晶粒相鄰，且TPV包括第一導電層與第二導電層。第一導電層填入TPV的第一部份，且第二導電層填入TPV的第二部份。半導體晶粒封裝亦包括重佈線結構，且重佈線結構包括重佈線層(RDL)。TPV與半導體晶粒電性連接至RDL，且RDL使半導體晶粒具有扇出式結構。
在某些實施例中，半導體晶粒封裝包括半導體晶粒與形成其中的TPV。TPV與半導體晶粒相鄰，其中TPV包括導電層與凹陷。半導體晶粒封裝亦包含重佈線結構，其包括重佈線層(RDL)。TPV與半導體晶粒電性連接至RDL，且RDL使半導體晶粒具有扇出式結構。凹陷與RDL分別位於導電層的相反兩端上。
在某些實施例中，封裝上封裝(PoP)裝置包括第一晶粒封裝，其包括第一半導體晶粒與TPV。TPV與第一半導體晶粒相鄰，且TPV包括第一導電層與第二導電層。PoP裝置亦包含第二晶粒封裝，其包括第二半導體晶粒與外部連接物(具有焊料)。第二晶粒封裝的外部連接物接合至第一晶粒封裝的TPV。
雖然上述內容已詳述實施例與其優點，但應理解在不脫離申請專利範圍和實施例精神的前提下，可進行各種改變、替代、與變更。此外，申請專利範圍不限於上述內容中特定實施例的製程、機器、製作、組成、裝置、方法、和步驟。如本技術領域中具有通常知識者由本發明所知，根據本發明可用的方式與對應實施例，即可採用目前或未來研發之具有實質上相同功能或可達實質上相同結果的製程、機器、製作、組成、 裝置、方法或步驟。綜上所述，申請專利範圍包括上述製程、機器、製作、組成、裝置、方法、或步驟。此外，每個申請專利範圍均為個別實施例，且各種申請專利範圍和實施例的組合均屬本發明範疇。
Y‧‧‧區域
105‧‧‧基板
110、120’‧‧‧封裝
112、113、121‧‧‧半導體晶粒
114、116‧‧‧接合打線
117‧‧‧連接物
123‧‧‧成型化合物
126‧‧‧外部連接物
142’‧‧‧IMC層
203‧‧‧第一導電層
207‧‧‧第二導電層
212、214‧‧‧鈍化層
260’‧‧‧接合結構

Claims (11)

  1. 一種半導體晶粒封裝，包括：一半導體晶粒；一成型化合物，封裝至少部份的該半導體晶粒；一通過封裝通孔，形成於該成型化合物中，其中該通過封裝通孔與該半導體晶粒相鄰，其中該通過封裝通孔包括一第一導電層與一第二導電層，且其中該第一導電層填入該通過封裝通孔的一第一部份，且該第二導電層填入該通過封裝通孔的一第二部份；以及一重佈線結構，其中該重佈線結構包括一重佈線層，其中該通過封裝通孔與該半導體晶粒電性連接至該重佈線層，且其中該重佈線層使該半導體晶粒具有扇出式結構。
  2. 如申請專利範圍第1項所述之半導體晶粒封裝，其中該第一部份之高度介於約0.1μm至約30μm之間，且其中該第二部份之高度介於約50μm至約300μm之間。
  3. 如申請專利範圍第1項所述之半導體晶粒封裝，其中該通過封裝通孔在遠離該重佈線層的一側，自該成型化合物之上表面向下凹陷約0.1μm至約30μm之間。
  4. 如申請專利範圍第1項所述之半導體晶粒封裝，其中一第三導電層與該第一導電層相鄰，且該第三導電層與該第二導電層之間隔有該第一導電層，且其中該第三導電層之組成為焊料。
  5. 如申請專利範圍第1項所述之半導體晶粒封裝，其中該第一導電層之組成係鎳、鉑、錫、或錫合金，其中錫合金包含 銀、銅、鉍、或上述之組合，且其中該第二導電層之組成為銅。
  6. 一種半導體晶粒封裝，包括：一半導體晶粒；一通過封裝通孔，形成於該半導體晶粒封裝中，其中該通過封裝通孔與該半導體晶粒相鄰，其中該通過封裝通孔包括一導電層與一凹陷；以及一重佈線結構，其中該重佈線結構包括一重佈線層，其中該通過封裝通孔與該半導體晶粒電性連接至該重佈線層，且該再佈線層使該半導體晶粒具有扇出式結構，且其中該凹陷與該重佈線層分別位於該導電層的相反兩端上。
  7. 一種封裝上封裝裝置，包括：一第一晶粒封裝，包括：一第一半導體晶粒；一通過封裝通孔，其中該通過封裝通孔與該第一半導體晶粒相鄰，其中該通過封裝通孔包括一第一導電層與一第二導電層；以及一第二晶粒封裝，包括：一第二半導體晶粒；以及一外部連接物，具有一焊料；其中該第二晶粒封裝的該外部連接物接合至該第一晶粒封裝的該通過封裝通孔。
  8. 如申請專利範圍第7項所述之封裝上封裝裝置，其中該第二晶粒封裝的該外部連接物接合至該通過封裝通孔的該第一 導電層。
  9. 如申請專利範圍第7項所述之封裝上封裝裝置，其中該焊料填入部份該通過封裝通孔，並形成一金屬間化合物於一成型化合物的表面下，其中該成型化合物圍繞該通過封裝通孔與該半導體晶粒。
  10. 如申請專利範圍第7項所述之封裝上封裝裝置，其中該第一晶粒封裝更包括：一重佈線結構，包括一重佈線層，其中該通過封裝通孔與該半導體晶粒電性連接至該重佈線層，且其中該重佈線層使該半導體晶粒具有扇出式結構。
  11. 如申請專利範圍第7項所述之封裝上封裝裝置，其中該第一導電層之組成係鎳、鉑、錫、或錫合金，且錫合金包括銀、銅、鉍、或上述之組合，且其中該第二導電層之組成係銅。
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