JP2014112606A - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP2014112606A JP2014112606A JP2012266524A JP2012266524A JP2014112606A JP 2014112606 A JP2014112606 A JP 2014112606A JP 2012266524 A JP2012266524 A JP 2012266524A JP 2012266524 A JP2012266524 A JP 2012266524A JP 2014112606 A JP2014112606 A JP 2014112606A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 179
- 239000000758 substrate Substances 0.000 claims abstract description 379
- 239000011347 resin Substances 0.000 claims description 58
- 229920005989 resin Polymers 0.000 claims description 58
- 230000017525 heat dissipation Effects 0.000 claims description 16
- 239000000463 material Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 239000000853 adhesive Substances 0.000 description 16
- 230000001070 adhesive effect Effects 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 239000010949 copper Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000005855 radiation Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000005242 forging Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000007530 organic bases Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H01L2924/161—Cap
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Abstract
【解決手段】接続基板12a,12bは、中間基板13をパッケージ基板11から離間させる。これにより、パッケージ基板11の上面と中間基板13の下面との間には、半導体チップ14e,14fを収容可能な空間が形成される。そして、中間基板13の上面に半導体チップ14a〜14dを実装し、中間基板13の下面に半導体チップ14e,14fを実装する。
【選択図】図1
Description
なお、添付図面は、特徴を分かりやすくするために便宜上特徴となる部分を拡大して示している場合があり、寸法,比率などは実際と異なる場合がある。また、断面図では、各部材の断面構造を分かりやすくするために、一部のハッチングを省略している。
図2に示すように、半導体パッケージ10は、実装基板(例えば、マザーボード)MBの1つの主面(図において上面)に実装される。
図2に示すように、接続基板12a,12bは、中間基板13をパッケージ基板11から離間させる。これにより、パッケージ基板11の上面と中間基板13の下面との間には、半導体チップ14e,14fを収容可能な空間が形成される。これにより、中間基板13の下面に半導体チップ14e,14fを実装することができ、中間基板13の上面のみに半導体チップを実装する場合と比べて中間基板13に対する半導体チップの実装密度を高くすることができる。
図5(a)に示すように、中間基板13の上面及び下面に半導体チップ14a〜14fが実装される。例えば、中間基板13の上面と下面に半導体チップ14a〜14fが接着剤等により接着され、例えば250℃〜270℃のリフロー処理によってバンプ24,25により接続される。そして、中間基板13と半導体チップ14a〜14fの間にアンダーフィル樹脂33,34が形成される。アンダーフィル樹脂33,34は、加熱処理(例えば、150℃〜200℃)により硬化される。
(1−1)接続基板12a,12bは、中間基板13をパッケージ基板11から離間させる。これにより、パッケージ基板11の上面と中間基板13の下面との間には、半導体チップ14e,14fを収容可能な空間が形成される。これにより、中間基板13の下面に半導体チップ14e,14fを実装することができ、中間基板13の上面のみに半導体チップを実装する場合と比べて中間基板13に対する半導体チップの実装密度を高くすることができる。
なお、本実施形態において、上記実施形態と同じ部材については同じ符号を付し、その説明の一部または全てを省略する。
図8(a)に示すように、中間基板13の上面及び下面に半導体チップ14a〜14fが実装される。例えば、中間基板13の上面と下面に半導体チップ14a〜14fが接着剤等により接着され、例えば250℃〜270℃のリフロー処理によってバンプ24,25により接続される。そして、中間基板13と半導体チップ14a〜14fの間にアンダーフィル樹脂33,34が形成される。アンダーフィル樹脂33,34は、加熱処理(例えば、150℃〜200℃)により硬化される。
(2−1)有機基板である接続基板41a,41bを有する半導体パッケージ40において、第1の実施形態における効果と同様の効果を得ることができる。
なお、本実施形態において、上記実施形態と同じ部材については同じ符号を付し、その説明の一部または全てを省略する。
図10に示すように、放熱カバー52の内側には、パッケージ基板11、2つの接続基板12a,12b、中間基板13、6個の半導体チップ14a〜14fが配設されている。放熱板51は、中間基板13の下面に実装された半導体チップ14e,14fの下面とパッケージ基板11の上面との間に配設されている。
図10に示すように、中間基板13の上面に実装された半導体チップ14a〜14dは、熱伝導部材56を介して放熱カバー52に熱的に接続される。従って、半導体チップ14a〜14dにおいて発生する熱は、熱伝導部材56を介して放熱カバー52へ伝達され、その放熱カバー52から大気中へ放熱される。これにより、半導体チップ14a〜14dにて発生する熱が効率良く放熱され、半導体チップ14a〜14dの温度上昇が抑制される。
(3−1)中間基板13の下面に実装された半導体チップ14e,14fとパッケージ基板11の間に放熱板51を配設し、その放熱板51を熱伝導部材55を介して半導体チップ14e,14fと接続した。従って、半導体チップ14e,14fは熱伝導部材55を介して放熱板51と熱的に接続されるため、半導体チップ14e,14fの熱を効率良く放熱することができる。
・上記各実施形態において、中間基板13の下面に実装した半導体チップ14e,14fにおいて発生する熱を、例えばパッケージ基板11に放熱するようにしてもよい。この場合、熱伝導性の優れた接着シートやアンダーフィル樹脂を用いることができる。
・上記各実施形態において、中間基板13に実装される半導体チップの形状、数を適宜変更してもよい。
・半導体チップ14は、平面視で中間基板13と接続基板12a,12bとが重複する領域に跨って設けられていてもよい。
・第3の実施形態に対して、放熱カバー52を複数の部材から構成するようにしてもよい。
12a,12b 接続基板
41a,41b 接続基板
13 中間基板
14a〜14f 半導体チップ
21a〜25 バンプ
31a〜34 アンダーフィル樹脂
51 放熱板
52 放熱カバー
53〜56 熱伝導部材
61a,61b,63 接着シート
62 アンダーフィル樹脂
Claims (9)
- 第1の配線基板と、
第1主面に第1の半導体チップが実装され、第2主面に第2の半導体チップが実装された第2の配線基板と、
前記第1の配線基板の第1主面に実装され、前記第1の配線基板の第1主面に形成されたパッドと、前記第2の配線基板の第2主面に形成されたパッドとを電気的に接続する2つの接続基板と、
を有し、
2つの前記接続基板は、前記第2の配線基板の対向する一対の辺に沿って延びる矩形状に形成されてなること、
を特徴とする半導体パッケージ。 - 2つの前記接続基板は、前記第2の配線基板の対向する一対の辺から外側に突出するように形成され、
前記第2の配線基板と2つの前記接続基板と間には、アンダーフィル樹脂が充填されてなること、
を特徴とする請求項1に記載の半導体パッケージ。 - 前記第2の配線基板の第1主面に複数の前記第1の半導体チップが実装され、
前記複数の第1の半導体チップは、前記第1の配線基板の対向する一対の辺に沿って延びる長方形状に形成され、
2つの前記接続基板は、前記複数の第1の半導体チップが延びる方向と平行な方向に沿って延びるように形成されてなること、
を特徴とする請求項1又は2に記載の半導体パッケージ。 - 前記第2の半導体チップは、複数の前記第1の半導体チップ間の間隙に対応する位置に配置されていること、
を特徴とする請求項3に記載の半導体パッケージ。 - 前記第2の半導体チップは、前記第2の配線基板の対向する一対の辺と直交する方向に沿って延びる長方形状に形成されたこと
を特徴とする請求項3に記載の半導体パッケージ。 - 前記第2の半導体チップと前記第1の配線基板との間に配設され、前記第2の半導体チップと熱的に接続された第1の放熱部材を有すること、
を特徴とする請求項1〜5のうちの何れか一項に記載の半導体パッケージ。 - 前記第1の放熱部材は、矩形板状に形成されるとともに、前記第1の放熱部材の両端部のうちの少なくとも一方は前記第2の配線基板の端部から突出するように形成され、
前記半導体パッケージは更に、
前記放熱部材の突出する端部と熱的に接続された第2の放熱部材を有すること、
を特徴とする請求項6に記載の半導体パッケージ。 - 前記第2の放熱部材は、前記第1配線基板に接続され、前記第1の半導体チップを覆うように形成され、
前記第1の半導体チップは前記第2の放熱部材と熱的に接続されること、
を特徴とする請求項7記載の半導体パッケージ。 - 前記第1の放熱部材は、前記第2の配線基板と前記第1の配線基板の間に配置され前記第2の配線基板に実装された半導体チップの熱を前記第1の配線基板に伝導する熱伝導部材であること、
を特徴とする請求項6に記載の半導体パッケージ。
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JP2012266524A JP2014112606A (ja) | 2012-12-05 | 2012-12-05 | 半導体パッケージ |
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