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TWI646639B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI646639B
TWI646639B TW103131554A TW103131554A TWI646639B TW I646639 B TWI646639 B TW I646639B TW 103131554 A TW103131554 A TW 103131554A TW 103131554 A TW103131554 A TW 103131554A TW I646639 B TWI646639 B TW I646639B
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TW
Taiwan
Prior art keywords
package
solder
metal
metal post
seed pattern
Prior art date
Application number
TW103131554A
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English (en)
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TW201517222A (zh
Inventor
金東先
柳盛旭
李知行
Original Assignee
Ｌｇ伊諾特股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020130110974A external-priority patent/KR102109042B1/ko
Priority claimed from KR1020130115333A external-priority patent/KR102091619B1/ko
Priority claimed from KR1020130115332A external-priority patent/KR102093927B1/ko
Application filed by Ｌｇ伊諾特股份有限公司 filed Critical Ｌｇ伊諾特股份有限公司
Publication of TW201517222A publication Critical patent/TW201517222A/zh
Application granted granted Critical
Publication of TWI646639B publication Critical patent/TWI646639B/zh

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本發明提供一種半導體封裝體，其包括：一下層封裝體，其用以安裝元件；一金屬柱，其連接該下層封裝體，且包含至少一金屬材料部；以及一上層封裝體，其用以安裝元件，並經由一焊錫球連接至該金屬柱。

Description

半導體封裝
本發明主張關於2013年09月16日申請之韓國專利案號10-2013-0110974以及2013年09月27日申請之韓國專利案號10-2013-0115332之優先權以及2013年09月27日申請之韓國專利案號10-2013-0115333之優先權。藉以引用的方式併入本文用作參考。
本發明實施例係關於一種半導體封裝技術。
根據半導體技術的發展，電子裝置須符合微型化以及輕巧的特性以滿足使用者的需求，因此，一種製作同類型或不同類型的半導體晶片成為一單元封裝的多晶片(nulti-chip)封裝技術已被廣泛使用。相較於執行半導體晶片封裝，就一封裝尺寸或重量以及一安裝程序而言，該多晶片封裝體主要應用在可攜式通訊終端設備，以期達到輕薄短小的需求。
在各種多晶片封裝技術中，一種將一封裝基板堆疊在另一封裝基板之上的方法稱之為層疊封裝技術(package on package，下文中稱之為“PoP”)。隨著半導體封裝技術的發展，其容量變得更大、厚度變得更薄以及尺寸變得更小，近年來堆疊晶片的數目也逐漸增加。
習用的封裝方法係使用一焊錫球印刷製程以及一迴焊製程(reflow process)連接兩封裝體，或者使用一迴焊製程連接一上部封裝體至下部封裝體。該方法係在該下層封裝體塑模(molding)後，(透過塑模穿孔方法)藉由對一塑模部執行一雷射鑽孔製程，並經由該穿孔印刷一焊錫球，再藉由形成穿孔往上至下層封裝體的一PoP焊接點，以安裝記憶晶片(memory dies)。
然而，為了實現高集成以及高效能的封裝體在封裝產品上，晶片配置數目已增加或者嘗試安裝被動元件等方法也已實行。為了實現這需求，更進一步增加兩封裝體之間的距離係重要的技術。
然而，一般的半導體封裝技術，當為了增加兩封裝體之間的距離而增加一焊錫球的一尺寸或一高度時，該焊錫球將容易產生裂縫或倒塌的問題。
本發明已可解決上述問題，而本發明的一觀點係藉由增加一上封裝體及一下封裝體之間的距離以增加所配置晶片的數目，及上封裝體及下封裝體之間優異的黏合可靠性技術，以提供一種高密度的半導體封裝體。
為了解決上述問題，根據本發明一實施例的觀點，其提供一種半導體封裝，包括：一下封裝體，其係用以安裝各元件；一金屬柱，其係用以連接至該下封裝體，且包括至少一金屬材料部；以及一上封裝體，其係用以安裝各元件，且其係經由一 焊錫球連接至該金屬柱。
根據本發明另一實施例，該金屬材料部可有一表面處理層形成在此之上表面。
根據本發明再另一實施例，該表面處理層可形成在該金屬柱的一上表面以及一側面。
根據本發明再另一實施例，該表面處理層可以金(Au)或鎳(Ni)至少其中一種金屬材料製作。
根據本發明另一實施例，該連接至焊錫球的金屬柱之一端，其形成的寬度小於另一端的寬度。
根據本發明另一實施例，該金屬柱形成的寬度係從連接至焊錫球的一端逐漸往另一端增加。
根據本發明另一實施例，該金屬柱可形成的寬度為另一端寬度的50%~90%。
根據本發明另一實施例，該金屬柱的一表面，其係以相對於下封裝體基板表面的一縱向的斜5°~45°角度形成。
根據本發明另一實施例，該連接至焊錫球的金屬柱之一端點可進入該焊錫球內。
根據本發明另一實施例，該金屬柱可以：銅(Cu)、錫(Sn)、鉛(Pb)以及銀(Ag)當中至少其中一種材料製作而成。
根據本發明另一實施例，該金屬柱可包括：一第一金屬材料的一焊錫部，以及一第二金屬材料的一金屬材料部。
根據本發明另一實施例，該焊錫部可由錫(Sn)和銅 (Cu)的合金材料，或者錫(Sn)和銀(Ag)的合金材料製作而成。
根據本發明再另一實施例，該焊錫部的熔點可設定在230℃~250℃之間。
根據本發明再另一實施例，該下層封裝體可包括：一基板以及形成在該基板上的一第一種子圖案部，而該金屬柱可形成在該第一種子圖案部。
根據本發明再另一實施例，該半導體封裝體可擴充包括一阻焊圖案(solder resist pattern)，其係形成在該第一種子圖案部，以便該第一種子圖案的一上表面可顯露在外。
300‧‧‧下層封裝體
310‧‧‧下層封裝體基板
350‧‧‧外部端點
370‧‧‧下部元件
400‧‧‧上層封裝體
410‧‧‧上層封裝體基板
430‧‧‧上部元件
442‧‧‧黏合金屬導線
500‧‧‧金屬柱
501‧‧‧焊錫球
510‧‧‧焊錫部
520‧‧‧表面處理層
530‧‧‧第一種子圖案部
535‧‧‧第二種子圖案部
540‧‧‧阻焊圖案
541‧‧‧阻焊層
610‧‧‧光阻層
611‧‧‧光阻圖案
圖1係根據本發明一實施例之一半導體封裝體的剖視圖。
圖2係根據本發明實施例之半導體封裝體之一金屬柱的剖視圖。
圖3係根據本發明另一實施例之一半導體封裝體的一金屬柱剖視圖。
圖4~圖12係根據本發明實施例的半導體封裝體之金屬柱製作方法說明圖。
圖3~圖21係根據本發明另一實施例的半導體封裝體之金屬柱製作方法說明圖。
圖22係根據再另一實施例之一半導體封裝體的一金屬柱剖視圖。
本發明個實施例將參考配合圖示於下文中詳細說明之，並繪示個典型實施例。然而，本發明不同形式的實施例將 不受限於此處所陳述的各實施例。在以下說明中，值得注意的是，當一般的元件功能及元件的詳細說明與本發明有關會造成本發明主旨不清楚時，這些元件的詳細說明將予以省略。再者，理應理解的是，圖示中的元件的之形與尺寸是可被誇示的，以方便本發明結構的說明，而非反映元件實際的尺寸。
圖1係根據本發明一實施例之一半導體封裝體的一剖視圖。
參考圖1，根據本發明一實施例之半導體封裝體，其可配置成一種層疊封裝(Package on Package，POP)型式，其中一上層封裝體400係層疊在一下層封裝體300之上。這樣的話，該上層封裝體與下層封裝體可相互電性連接。
該半導體封裝體包括：下層封裝體300、上層封裝體400以及一金屬柱500。
在該下層封裝體300內，至少有一下部元件370被安裝在一下層封裝體基板310上；且在該上層封裝體400內，至少有一上部元件430被安裝在一上層封裝體基板410上。同時，該上部元件430可由一半導體所組成。
這時，該下層封裝體基板310及該上層封裝體基板410兩者至少任何之一可組合成一印刷電路板(printed circuit board,PCB)。
如一例而言，該下層封裝體300可包括下層封裝體基板310，以及安裝在該下層封裝基板的下部元件370。當該下部 元件370配置複數個時，該複數個下部元件370可以藉由插入一絕緣材料層於其間的方式層疊配置。
外部端點350以一焊錫球形成，其電性連接該半導體封裝體至一外部裝置，其並可配置在該下層封裝體基板310的一下表面。
同理，該上層封裝體400可包括該上層封裝體基板410以及安裝在該上層封裝體基板410之一上部表面的上部元件430。當該上部元件430配置複數個時，該複數個上部元件430可藉由插入一絕緣材料層於其間的方式層疊配置。
該上部元件430以及該上層封裝體基板410可經由複數個黏合金屬導線442使其相互電性連接。
該金屬柱500連接至該下層封裝體300，其配置如上述說明。
更具體而言，一第一種子圖案部530可形成在該下層封裝體300的基板上，並且該金屬柱500可形成在該第一種子圖案部530上。
此時，該金屬柱500可包括至少一金屬材料部，且在此時，該金屬柱可由一第一金屬材料的一焊錫部510以及一第二金屬材料的一金屬材料部，或由者該表面處理層520及該金屬材料部所組成。
根據本發明實施例，該焊錫部510可以錫(Sn)及銅(Cu)的合金或者是錫(Sn)及銀(Ag)的合金材料製作而成，以便製 成具有一熔點介於230℃至250℃的高熔點焊錫材料，且該金屬材料部可由一銅材料製作而成。
當使用一般焊錫材料時，該一般焊錫材料的熔點為210℃至220℃。然而，如本發明之實施例，當該焊錫部510係由熔點230℃至250℃的金屬材料之高熔點焊錫材料所製成時，其可達到優異的黏合可靠性，所以層疊在上層封裝體400之上時，可確保一穩定的製程良率。
且，如圖1所繪示，該焊錫部510可配置在該下層封裝體300的一較高的表面並朝上伸出，且高於位於下層封裝體300一阻焊圖案540。
該金屬柱500如上述配置，其可經由一焊錫球501連接至上層封裝體400。
當配置包含高熔點焊錫材料之焊錫部510的金屬柱500後，以薄片層疊成製程方式應用在上層封裝體400，其穩定良率可以被確保，且藉由增加該上層封裝體400及該下層封裝體300之間的一距離，高密度基底的半導體晶片層疊可被製作，並且可形成具改善的可靠性與穩定性的半導體封裝體。
同時，當該金屬柱500係由該表面處理層520以及該金屬材料部所組成時，該表面處理層520可以使用一金屬材料做為一電鍍層形成。更具體地來說，該表面處理層520可以金(Au)或鎳(Ni)至少其中一種材料製作而成。
如本發明實施例所示，當該表面處理層520係形成 在該金屬柱500的表面時，其與該上層封裝體400的黏合可靠性可增進，且以薄片層疊製程方式應用在上層封裝體400，其穩定良率可以確保。此外，由於該金屬柱500係防氧化的，所以該半導體封裝體的可靠度可被確保。
同時，該金屬柱500，其係以連接至該下層封裝體300一側面端點之一寬度，大於連接至該上層封裝體400一側面端點之寬度的配置方式形成。
更具體地來說，如圖1所繪示，該金屬柱500，其形成於連接至該焊錫球501之一端點的一寬度小於相反的另一端點的一寬度，且在此時，該金屬柱500的寬度係以從另一端點往該一端點逐漸縮小的方式配置。
也就是，該金屬柱的500寬度可以從上部往連接至下層封裝體基板310側面寬度逐漸縮小的方式配置。
此時，當該金屬柱500的一端點之寬度，以該金屬柱另一端點的50%或更小尺寸形成時，或者該金屬柱500係以與該下層封裝體基板310表面45°或更小的角度傾斜配置時，則該金屬柱與焊錫球501黏合可靠度將會產生問題。
所以，該金屬柱500係以一端的寬度為另一端寬度的50至90%配置，或者一縱向表面與該下層封裝體基板表面的垂直方向以5°至45°傾斜，以便該金屬柱500與該焊錫球50的黏合可靠度可確保。
此時，該金屬柱500可以銅(Cu)製作。
該金屬柱500，形成如上述說明，其經由該焊錫球501，以該金屬柱500之一上部端至少一部份插入至該焊錫球501的方法，連接至該上層封裝體400內。
且，由於該金屬柱500形成在一表面上，與該下層封裝體基板310的表面垂直方向相一致，故沒有一階錐(stepped cone)，這樣有利於均勻地維持電子特性，並且只要小量的焊錫球501，其與該上層封裝體400的黏合強度即可改善。
如此，根據本發明實施例，其金屬柱配置為：該金屬柱的一端點寬度(a)為另一端點寬度的50%至90%，該表面的縱向係以5°至45°的角度與該下層封裝體基板的一表面垂直方向相傾斜，該形成在上層封裝體基板410表面的焊錫球501之用量可減少，且因使用焊錫球501圍繞該金屬柱500的黏合方法，黏合性的可靠度可更進一步增進。
圖2係根據本發明實施例之半導體封裝體的一金屬柱剖視圖，且圖2之實施例繪示一結構，其中該金屬柱500的焊錫部510朝上突出高於一阻焊圖案540。
根據本發明實施例之半導體封裝體的金屬柱結構外形將參考圖2說明之。
如圖2所繪示，該第一種子圖案部530係形成在該下層封裝體基板310上，且該阻焊圖案540係形成在該第一種子圖案部530的一周邊部份。
一第二種子圖案部535，其形成在該阻焊圖案540 上，並連接至該第一種子圖案部530。
同時，該金屬柱500係形成在該第二種子圖案部535上。
此時，該金屬柱500可包括：該焊錫部510以及金屬材料部或表面處理層520，其可形成在該金屬柱500的上端點。該金屬柱500朝上突出並高於該阻焊圖案540。
圖3係根據本發明另一實施例之半導體封裝體之一金屬柱的一剖視圖，該圖3實施例繪示一結構，其中該金屬柱的焊錫部510係以和該阻焊圖案540相同平面高度配置。
根據本發明另一實施例，該半導體封裝體之金屬柱的配置將參考圖3說明之。
如圖3所繪示，該第一種子圖案部530係形成在該下層封裝基板310上，且該阻焊圖案540係形成在該第一種子圖案部530的該周邊部分。
該第二種子圖案部535連接至該第一種子圖案部530，且其係形成在該阻焊圖案540上。且在此時，該第二種子圖案部535係形成在該阻焊圖案540除了一上表面之外的一側面。
該金屬柱500係形成在該第二種子圖案部535上，且在此時，該金屬柱500包括該焊錫部510以及該金屬材料部，且該焊錫部510係以和阻焊圖案540相同平面的高度配置。
該焊錫部510可以熔點在230℃至250℃的高熔點焊錫材料製作成，如錫(Sn)和銅(Cu)的一合金，或是錫(Sn)和銀 (Ag)的一合金，且該金屬材料部可以一銅材料製作成。
圖4~圖12繪示說明根據本發明實施例之一半導體封裝體的金屬柱之製作方法，也就是，用以說明根據圖2實施例之半導體封裝體的金屬柱之製作方法。
如圖4所繪示，該第一種子圖案部530係形成在該下層封裝體基板310上，且該阻焊層541係形成在該第一種子圖案部530上，該第一種子圖案部530的形成如上述說明。
接下來，如圖5所繪示，該阻焊圖案部540係藉由圖案化該阻焊層在該第一種子圖案部530上而形成的。
如圖6所繪示，該第二種子圖案部535係形成在該阻焊圖案540上，該阻焊圖案540的形成如上述說明。
接下來，如圖7所繪示，一光阻層610形成在該第二種子圖案部535上，且如圖8所繪示，一光阻圖案611藉由薄片層疊以及對該光阻層610實行曝光及顯影等製程而形成。
同時，該光阻層610以及該各光阻圖案611可以一乾式薄膜光阻(dry film photo resist，DFR)製作而成。
接下來，如圖9所繪示，該焊錫部510可形成在該光阻圖案611與該毗鄰光阻圖案之間的第二種子圖案部535之上，其可使用一高熔點焊錫材料或金屬材料部形成。
這時，根據本發明實施例，該焊錫部510可形成在一熔點在230℃至250℃之高熔點焊錫材料，如：一錫(Sn)和銅(Cu)的合金材料，或者一錫(Sn)和銀(Ag)的合金材料製作而成。
接下來，如圖10所繪示，該金屬材料部係使用一金屬材料藉由電鍍方法形成在該焊錫部510上。此時，該金屬材料部可由銅材料製作成。
接下來，藉由移除該光阻圖案611，如圖11所繪示，該第二種子圖案部535的圖形曝光至該阻焊層541，並且藉由移除該曝光後的第二種子圖案部535，如圖12所繪示，該金屬柱500即可完成。
根據本發明實施例，藉由如上述之金屬柱的配置，該上層封裝體與該下層封裝體的一距離得以增加，以便該半導體晶片可以高密度層疊方法製作，且該半導體封裝體可增進可靠度與穩定性。
圖13~圖21繪示說明根據本發明另一實施例半導體封裝體之金屬柱的製作方法，也就是，根據圖3實施例圖示說明該半導體封裝體之金屬柱。
如圖13所繪示，該第一種子圖案部530係形成在該下層封裝體基板310上，該阻焊層541係形成在該第一種子圖案部530上。且如圖14所繪示，該阻焊圖案540係藉由圖案化該阻焊層541在該第一種子圖案部530上形成的。
如圖15所繪示，該第二種子圖案部535係形成在該阻焊圖案540上，阻焊圖案540的形成如上述說明，並繪示於圖16，該光阻層610係形成在該第二種子圖案部535上，如圖17所繪示，該光阻圖案611係以對光阻層610薄片層疊、曝光及顯影等製程方 法形成。
這時，該光阻層610以及該光阻圖案611可以乾式薄膜光阻(Dry Film Photo Resist，DFR)形成。
接下來，如圖18所繪示，該金屬柱500係藉由填充一金屬材料至該第一種子圖案部530以及介於該光阻圖案611與該毗鄰光阻圖案之間的第二種子圖案部535而形成，且可以使用銅(Cu)做為形成該金屬柱500的一金屬材料。
接下來，如圖19所繪示，藉由移除該光阻圖案611使該第二圖案部535暴露出，如圖20所繪示，藉由移除該暴露的第二種子圖案部形成該金屬柱。
接下來，如圖21所示，該表面處理層520可形成在該金屬柱500的上表面及側面。
同時，至少使用金(Au)或鎳(Ni)其中一種金屬材料以形成該表面處理層520。
圖22係根據本發明再另一實施例之一半導體封裝體金屬柱的剖視圖。
如圖22所繪示，該金屬柱500可以連接至焊錫球520的一端點之寬度(a)小於另一端點之寬度(b)的配置方式形成，且在此時，該金屬柱500可以其寬度從另一端往一端逐漸縮小的方法配置。
也就是，該金屬柱500可以一上部的寬度(a)往連接至下層封裝體基板310的側面寬度(b)逐漸縮小之方式配置。
在此時，當該金屬柱500的一端點的寬度(a)係以該金屬柱500的另一端寬度(b)的50%或更小的尺寸形成時，或者當該金屬柱500係以和該下層封裝體基板310的表面傾斜45°或更小的角度配置時，則對於焊錫球501黏合可靠度將會產生問題。
因此，該金屬柱500係以一端點的寬度(a)為另一端點寬度(b)的50至90%配置，或者其縱向的表面與該下層封裝體一的一基板的一表面的垂直方向傾斜5°至45°的話，這樣的話，該金屬柱500與該焊錫球501的黏合可靠度可確保。
這時，該金屬柱500係以銅(Cu)形成，並且該金屬柱500包含：銅(Cu)、錫(Sn)、鉛(Pb)以及銀(Ag)至少其中一種材料配置。
該金屬柱500，如上述說明形成，其經由該焊錫球501連接至該上層封裝體400，如此，至少該金屬柱500的上端點可嵌入至該焊錫球501內。
且，由於該金屬柱500係形成在該下層封裝體基板310的表面上，其方向與基板的一垂直方向一致，這樣的話不會有階錐的問題，如此有益於電特性均勻維持，並且只要使用少量的焊錫球501其與該上層封裝體400的黏合強度便可改進。
如上述說明，根據本發明之實施例，因該金屬柱以其一端的寬度(a)為另一端寬度(b)的50%至90%配置，其縱向表面與該下層封裝體一基板的該表面的垂直方向以5°至45°的角度傾斜，則形成在該上層封裝體基板410上之焊錫球501的用量可降 低，且因在該金屬柱500係以焊錫球501圍繞黏合方式形成，其黏合的可靠度可更加提高。
同時，該金屬柱500的高度，其形成高於配置在該下層封裝體300之半導體晶片的高度，且在此時，考慮該半導體晶片的尺寸，該金屬柱的一高度形成的範圍為50~400μm之間，因該金屬柱500的緣故，以便該半導體晶片可配置在該上層封裝體400與該下層封裝體300之間間隔開的空間，因此使得該半導體晶片可不與該上層封裝體400相接觸。
如上述說明，根據本發明一些實施例，介於該上層封裝體與下層封裝體之間的一距離增加，其所配置的晶片數量可增加，這樣的話可以實現高密度封裝，並且可提供上層封裝體與下層封裝體之間可靠的半導體封裝黏合力。
如上述說明，雖然已參考許多說明性實施例來描述實施例，但應理解，可由熟習此項技術者設計的許多其他修改及實施例將落入本揭示案之原理之精神及範疇內。因此，理應理解的是前述說明係闡釋本發明，且並不以此推論限制特殊實施例之揭示案。並且，對於揭示案實施例之修改，及其他實施例，均包括在附加專利申請範圍及其等效物之範疇內。

Claims (8)

  1. 一半導體封裝體，其包含：一下層封裝體，其係用以安裝元件；一金屬柱，其連接至下層封裝體，且包括至少一金屬材料部；以及一上層封裝體，其係用以安裝元件，且其經由一焊錫球連接至該金屬柱，其中該下層封裝體包含：一基板；一第一種子圖案部形成於該基板上，其中該金屬柱於該第一種子圖案部上；一阻焊圖案形成在該第一種子圖案部上，使該第一種子圖案部的一上表面的一部分可暴露在外；一第二種子圖案部形成在該阻焊圖案的一上表面外的一側，該第二種子圖案部連接第一種子圖案部且該第二種子圖案部的部分位於該阻焊圖案的上表面上；其中第二種子圖案部直接物理接觸該金屬柱的一側表面；以及其中第一種子圖案部直接物理接觸該金屬柱的一下表面。
  2. 如專利申請範圍第1項所述之半導體封裝體，其中該金屬柱係以連接至該焊錫球的一端點的寬度小於另一端的寬度方式配置，該金屬柱的另一端至焊錫球的該端點的該寬度逐漸減少。
  3. 如專利申請範圍第1項所述之半導體封裝體，其中該金屬柱該端的寬度為另一端寬度的50%至90%形成方式配置。
  4. 如專利申請範圍第1項所述之半導體封裝體，其中該金屬柱的縱向表面係以相對於該下層封裝體的該基板的一表面5°至45°的傾斜角度形成方式配置。
  5. 如專利申請範圍第1項所述之半導體封裝體，其中該金屬 柱包括以錫(Sn)形成於該第一種子圖案部上的一焊錫部，以及以銅(Cu)形成於該焊錫部上的一金屬材料部。
  6. 如專利申請範圍第5項所述之半導體封裝體，其中該其中焊錫部的一上表面的一寬度同於該金屬材料部的一下表面。
  7. 如專利申請範圍第2項所述之半導體封裝體，其中該焊錫部的熔點為230℃至250℃之間。
  8. 如專利申請範圍第5項所述之半導體封裝體，其中該第二種子圖案部直接物理接觸位於該阻焊圖案及該焊錫部之間的該焊錫部的一側表面，其中該第一種子圖案部直接物理接觸該焊錫部的一下表面。
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